Timing local streams: Improving timeliness in data prefetching

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2010, Pages 169-178

  Zhu, Huaiyu ^a   Chen, Yong ^a   Sun, Xian He ^a  

^a Illinois Institute of Technology   (United States)

Author keywords

cache memory; data prefetching; prefetching performance; prefetching simulation

Indexed keywords

CACHE POLLUTION; DATA PATTERNS; DATA-PREFETCHING; DATA-PREFETCHING TECHNIQUES; EXTENSIVE SIMULATIONS; LOCALIZATION TECHNIQUE; MEMORY REGION; PREFETCHES; PREFETCHING; PREFETCHING SIMULATION; PREFETCHING TECHNIQUES; PROGRAM COUNTERS; SIMULATION RESULT; TIMING INFORMATION;

HYDRAULICS; TIME MEASUREMENT;

CACHE MEMORY;

EID: 77954734107     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1810085.1810110     Document Type: Conference Paper

References (25)

1. DPC-1 Homepage. http://www.jilp.org/dpc, 2008.
2. T.-F. Chen and J.-L. Baer. Effective hardware based data prefetching for high-performance processors. IEEE Trans. Computers, 44(5):609-623, 1995.
3. Y. Chen, S. Byna, and X.-H. Sun. Data access history cache and associated data prefetching mechanisms. In SC, 2007.
4. Y. Chen, H. Zhu, and X.-H. Sun. An adaptive data prefetcher for high-performance processors. In CCGrid, 2010.
5. Y. Chou. Low-cost epoch-based correlation prefetching for commercial applications. In MICRO, 2007.
6. F. Dahlgren, M. Dubois, and P. Stenström. Fixed and adaptive sequential prefetching in shared memory multiprocessors. In ICPP, pages 56-63, 1993.
7. P. Diaz and M. Cintra. Stream chaining: Exploiting multiple levels of correlation in data prefetching. In ISCA, pages 81-92, 2009.
8. J. Doweck. Inside Intel Core microarchitecture and smart memory access. Intel White Paper, 2006.
9. Z. Hu, M. Martonosi, and S. Kaxiras. Timekeeping in the memory system: Predicting and optimizing memory behavior. In ISCA, pages 209-220, 2002.
10. A. Jaleel, R. S. Cohn, C. keung Luk, and B. Jacob. CMP$im: a pin-based on-the-fly multi-core cache simulator. In 4th Annual Workshop on Modeling, Benchmarking and Simulation, pages 28-36, 2008.
11. D. Joseph and D. Grunwald. Prefetching using markov predictors. In ISCA, pages 252-263, 1997.
12. G. B. Kandiraju and A. Sivasubramaniam. Going the distance for TLB prefetching: An application-driven study. In ISCA, pages 195-206, 2002.
13. A.-C. Lai, C. Fide, and B. Falsafi. Dead-block prediction & dead-block correlating prefetchers. In ISCA, pages 144-154, 2001.
14. C.-K. Luk, R. S. Cohn, R. Muth, and et. al. Pin: building customized program analysis tools with dynamic instrumentation. In PLDI, 2005.
15. K. J. Nesbit, A. S. Dhodapkar, and J. E. Smith. AC/DC: an adaptive data cache prefetcher. In IEEE PACT, 2004.
16. K. J. Nesbit and J. E. Smith. Data cache prefetching using a global history buffer. In HPCA, 2004.
17. S. Palacharla and R. E. Kessler. Evaluating stream buffers as a secondary cache replacement. In ISCA, pages 24-33, 1994.
18. S. Somogyi, T. F. Wenisch, and et. al. Spatial memory streaming. In ISCA, 2006.
19. S. Somogyi, T. F. Wenisch, and et. al. Spatio-temporal memory streaming. In ISCA, 2009.
20. C. D. Spradling. SPEC CPU2006 benchmark tools. ACM SIGARCH Computer Architecture News, 2007.
21. S. Srinath, O. Mutlu, H. Kim, and Y. N. Patt. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers. In HPCA, pages 63-74, 2007.
22. X.-H. Sun, S. Byna, and Y. Chen. Server-based data push architecture for multi-processor environments. JCST, 22(5), 2007.
23. J. M. Tendler, J. S. Dodson, J. S. F. Jr., and et. al. POWER4 system microarchitecture. IBM Journal of Research and Development, 46(1):5-26, 2002.
24. T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsafi. Temporal streaming of shared memory. In ISCA, pages 222-233, 2005.
25. W. A. Wulf and S. A. McKee. Hitting the memory wall: implications of the obvious. ACM SIGARCH Computer Architecture News, 23(1):20-24, 1995.