Server-based data push architecture for multi-processor environments

Journal of Computer Science and Technology

Volumn 22, Issue 5, 2007, Pages 641-652

  Sun, Xian He ^a,b   Byna, Surendra ^a   Chen, Yong ^a  

^a Illinois Institute of Technology   (United States)

^b FERMI NATIONAL ACCELERATOR LABORATORY   (United States)

Author keywords

Cache memory; Evaluation; Modeling; Performance measurement; Simulation of multiple processor system

Indexed keywords

HIGH-END COMPUTING (HEC) MACHINES; MULTIPLE-PROCESSOR SYSTEMS; PERFORMANCE MEASUREMENT; SERVER-BASED DATA;

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA REDUCTION; MATHEMATICAL MODELS; SERVERS;

MULTIPROCESSING SYSTEMS;

EID: 34548803983     PISSN: 10009000     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11390-007-9090-y     Document Type: Article

References (42)

1. DARPA. High productivity computing systems (HPCS), vision: Focus on the lost dimension of HPC "User & system efficiency and productivity". http://www.darpa.mil/ipto/programs/hpcs/vision.htm.
2. John Hennessy, David Patterson. Computer Architecture: A Quantitative Approach. Fourth edition, Morgan Kaufmann, ISBN: 0123704901, 2006.
3. Wm A Wulf, Sally A McKee. Hitting the memory wall: Implications of the obvious. ACM SIGARPH Computer Architecture News, March 1995, 23(1): 20-24.
4. Chen T F, Baer J L. Effective hardware-based data prefetching for high performance processors. IEEE Transactions on Computers, 1995, 44(5): 609-623.
5. Dahlgren F, Dubois M, Stenström P. Fixed and adaptive sequential prefetching in shared-memory multiprocessors. In Proc. International Conference on Parallel Processing (ICPP), Los Alamitos, CA, USA, CRC Press, 1993, Vol.1, pp.56-63.
6. Fu J, Patel J H. Data prefetching in multiprocessor vector cache memories. In Proc. the 17th Annual International Symposium on Computer Architecture, Toronto, Canada, 1991, pp.54-63.
7. Joseph D, Grunwald D. Prefetching using Markov predictors. In Proc. the 24th International Symposium on Computer Architecture, Denver-Colorado, 1997, pp.252-263.
8. Gokul Kandiraju, Anand Sivasubramaniam. Going the distance for TLB prefetching: An application-driven study. In Proc. the International Symposium on Computer Architecture, Anchorage, Alaska, 2002, p.195.
9. Alexander T, Kedem G. Distributed predictive cache design for high performance memory system. In Proc. the 2nd International Symposium on High Performance Computer Architecture (HPCA), San Jose, CA, 1996, pp.254-263.
10. Collins J, Tullsen D, Wang H, Shen J. Dynamic speculative precomputation. In Proc. the 84th International Symposium on Microarchitecture, Austin, Texas, 2001, pp.306-317.
11. Wessam Hassanein, José Fortes, Rudolf Eigenmann. Data forwarding through in-memory precomputation threads. In Proc. the International Conference on Supercomputing (ICS), 2004.
12. Hughes C J. Prefetching linked data structures in systems with merged DRAM-logic [Thesis]. University of Illinois at Urbana-Champaign, Technical Report UIUCDCS-R-20012221, May 2000.
13. Liao S, Wang P, Wang H, Hoflehner G, Lavery D, Shen J. Post-pass binary adaptation tool for software-based speculative precomputation. In Proc. the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'02), Berlin, Germany, 2002, pp.117-128.
14. Chi-Keung Luk. Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors. In Proc. the 28th Annual International Symposium on Computer Architecture, Göeborg, Sweden, 2001, pp.40-51.
15. Amir Roth, Gurindar S Sohi. Speculative data-driven multithreading. In Proc. the 7th International Symposium on High Performance Computer Architecture, Nuevo Lenone, Mexico, 2001, p.37.
16. Craig Zilles, Gurindar Sohi. Execution-based prediction using speculative slices. In Proc. the 28th Annual International Symposium on Computer Architecture (ISCA), Göeborg, Sweden, 2001, pp.2-13.
17. Yang C L, Lebeck A R. Push vs. pull: Data movement for linked data structures. In Proc. the International Conference on Supercomputing (ICS), Santa Fe, New Mexcio, 2000, pp.76-186, pp.176-186.
18. James E Smith. Decoupled access/execute computer architectures. In Proc. the 9th Annual International Symposium on Computer Architecture (ISCA), Gold Coast, Queensland, 1982, pp,112-119.
19. Culler D, Singh J P, Gupta A. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, ISBN 1558603433, August 1998.
20. Xian-He Sun, Surendra Byna. Data-access memory servers for multi-processor environments. IIT CS TR-2005-001, November 2005, http://www.cs.iit.edu/~suren/research.html.
21. Burger D C, Austin T M, Bennett S. Evaluating future microprocessors: The SimpleScalar tool set. Technical Report 1308, University of Wisconsin-Madison Computer Sciences, 1996.
22. Surendra Byna, Xian-He Sun, William Gropp, Rajeev Thakur. Predicting the memory-access cost based on data access patterns. In Proc. the IEEE International Conference on Cluster Computing, San Diego, September 2004, pp.327-336.
23. Annavaram M, Patel J M, Davidson E S. Data prefetching by dependence graph pre-computation. In Proc. the 28th International Symposium on Computer Architecture (ISCA), Göeborg, Sweden, 2001, pp.52-61.
24. Kohout N, Choi S, Kim D, Yeung D. Multi-chain prefetching: Effective exploitation of inter-chain memory parallelism for pointer-chasing codes. In Proc. the 10th International Conference on Parallel Architectures and Compilation Techniques, Barcelona, Spain, 2001, pp.268-279.
25. Roth A, Moshovos A, Sohi G S. Dependence based prefetching for linked data structures. In Proc. the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, 1998, pp.115-126.
26. Ilya Ganusov, Martin Burtscher. Future execution: A hardware prefetching technique for chip multiprocessors. In Proc. the 14th Annual International Conference on Parallel Architectures and Compilation Techniques (PACT'OS), Saint Louis, MO, 2005, pp.350-360.
27. Conway J H, Guy R K. The Book of Numbers. SpringerVerlag, New York, 1996, ISBN: 038797993X.
28. Box GEPX, Jenkins G M, Reinsel G C. Time Series Analysis: Forecasting and Control. 3rd ed, Prentice Hall, 1994.
29. Jack Doweck. Inside Intel core microarchitecture and smart memory access. White paper, Intel Research website, Available online at http://download.intel. com/technology/architecture/sma.pdf, 2006.
30. Sun Microsystems. UltraSPARC IV Processor Architecture Overview. www.sun.com/processors/whitepapers/us4_whitepaper.pdf
31. IBM. Cell Broadband Engine resource center. http://www128.ibm.com/ developerworks/power/cell/.
32. Thomas R Puzak, A Hartstein, P G Emma, V Srinivasan. When prefetching improves/degrades performance. In Proc. the 2nd Conference on Computing Frontiers, Ischia, Italy, May 04-06, 2005, pp.342-352.
33. Standard Performance Evaluation Corporation. SPEC Benchmarks, http://www.spec.org/.
34. Jack J Dongarra, Jeremy Du Croz, Sven Hammarling, Iain Duff. A set of level 3 basic linear algebra subprograms. ACM Transactions on Mathematical Software, 1990, 16(1): 1-17.
35. John D McCalpin. Memory bandwidth and machine balance in current high performance computers. IEEE Technical Committee on Computer Architecture, 1995, http://www.cs.virginia.edu/stream.
36. Sherwood T, Perelman E, Calder B. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Proc. the International Conference on Parallel Architectures and Compilation Techniques, Barcelona, Spain, 2001, pp.3-14.
37. Dahlgren F, Dubois M, Stenström P. Sequential hardware prefetching in shared-memory multiprocessors. IEEE Transactions on Parallel and Distributed Systems, 1995, 6(7): 733-746.
38. Yue Liu, David R Kaeli. Branch-directed and stride-based data cache prefetching. In Proc. the 1996 International Conference on Computer Design, VLSI in Computers and Processors, October 7-9, 1996, pp.225-230.
39. Mowry T, Gupta A. Tolerating latency through softwarecontrolled prefetching in shared-memory multiprocessors. Journal of Parallel and Distributed Computing, June 1991, 12(2): 87-106.
40. Pai V S, Ranganathan P, Abdel-Shafi H, Adve S. The impact of exploiting instruction-level parallelism on sharedmemory multiprocessors. IEEE Transactions on Computers, February 1999, 48(2): 218-226.
41. Zhou H. Dual-core execution: Building a highly scalable single-thread instruction window. In Proc. the 2005 International Conference on Parallel Architectures and Compilation Techniques (PACT'05), Saint Louis, MO, 2005, pp.231-242.
42. Solihin Y, Lee J, Torrellas J. Using a user-level memory thread for correlation prefetching. In Proc. International Symposium on Computer Architecture, Anchorage, Alaska, May 2002, pp.171-182.