An adaptive data prefetcher for high-performance processors

CCGrid 2010 - 10th IEEE/ACM International Conference on Cluster, Cloud, and Grid Computing

Volumn , Issue , 2010, Pages 155-164

  Chen, Yong ^a   Zhu, Huaiyu ^a   Sun, Xian He ^a  

^a Illinois Institute of Technology   (United States)

Author keywords

Computer architecture; Data prefetching; High performance processors; Memory wall

Indexed keywords

ACCESS DELAY; ACCESS HISTORY; ACCESS PATTERNS; ACCESS TECHNOLOGY; ALGORITHM-LEVEL; COMPUTING POWER; COMPUTING SPEED; DATA-PREFETCHING; EFFECTIVE SOLUTION; EXTENSIVE SIMULATIONS; HARDWARE STRUCTURES; HIGH PERFORMANCE PROCESSORS; INSTRUCTIONS PER CYCLES; MEMORY WALL; PERFORMANCE BOTTLENECKS; PERFORMANCE COMPUTING; PERFORMANCE GAIN; PREFETCHING; PREFETCHING ALGORITHM; PROCESSOR SPEED; RUNTIMES; SIMPLESCALAR; SIMULATION RESULT;

ALGORITHMS; CLUSTER COMPUTING; COMPUTERS; GRID COMPUTING; SPEED;

COMPUTER ARCHITECTURE;

EID: 77954944200     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCGRID.2010.61     Document Type: Conference Paper

References (32)

1. B. Bloom. Space/Time Trade-offs in Hash Coding with Allowable Errors. Communications of the ACM, Vol. 13, No. 7, pp. 422-426, 1970.
2. D.C. Burger, T.M. Austin and S. Bennett. Evaluating Future Microprocessors: the SimpleScalar Tool Set. University of Wisconsin-Madison Computer Science Department Technical Report 1308, 1996.
3. S. Byna, Y. Chen and X.-H. Sun. Taxonomy of Data Prefetching for Multicore Processors", Journal of Computer Science and Technology (JCST), vol. 24, no. 3, pp. 405-417, 2009.
4. T.F. Chen and J.L. Baer. Effective Hardware-Based Data Prefetching for High Performance Processors. IEEE Trans. Computers, pp. 609-623, 1995.
5. Y. Chen, S. Byna and X.-H. Sun. Data Access History Cache and Associated Data Prefetching Mechanisms. In Proc. of the 2007 ACM/IEEE Supercomputing Conference, 2007.
6. F. Dahlgren, M. Dubois, and P. Stenstrom. Fixed and Adaptive Sequential Prefetching in Shared-memory Multiprocessors. In Proc. 1993 International Conference on Parallel Processing, pp. I56-I63, 1993.
7. F. Dahlgren, M. Dubois and P. Stenstrom. Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. on Parallel and Distributed Systems, Volume 6, Issue 7, pp.733-746, 1995.
8. J. Doweck. Inside Intel Core Micro-architecture and Smart Memory Access. Intel White Paper, 2006.
9. th International Parallel and Distributed Processing Symposium, 2005.
10. th Annual International Conference on Parallel Architectures and Compilation Techniques, 2005.
11. B. Goeman, H. Vandierendonck and K. Bosschere. Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency. In Proc. of 7th Intl. Symp. on High performance Computer Architecture, 2001.
12. J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. The 4th edition, Morgan Kaufmann, 2006.
13. N. P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. In Proc. of the 17th International Symposium on Computer Architecture, 1990.
14. D. Joseph and D. Grunwald. Prefetching Using Markov Predictors. In Proceedings of the 24th Annual Symposium on Computer Architecture, 1997.
15. H. Q. Le, W. J. Starke, J. S. Fields, F. P. O'Connell, D. Q. Nguyen, B. J. Ronchetti, W. M. Sauer, E. M. Schwarz and M. T. Vaden. IBM Power6 Microarchitecture. IBM Journal of Research and Development. Vol. 51, No. 6, pp. 639-662, 2007.
16. S.A. McKee. Reflections on the Memory Wall. In Proc. of Computing Frontiers (CF'04), 2004.
17. th Annual International Symposium on High Performance Computer Architecture, 2004.
18. th International Conference on Supercomputing, 2002.
19. L. Ramos, J. Briz, P. Ibañez and V. Viñals. Data Prefetching in a Cache Hierarchy with High Bandwidth and Capacity. In ACM Computer Architecture News, pages 37-44, 2007.
20. E. Rotenberg, S. Bennett, J. E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. In Proc. of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996.
21. Y. Sazeides and J. E. Smith. The Predictability of Data Values. In Proc. of the 30th Intl. Symp. on Microarchitecture, 1997.
22. K. Shen, M. Zhong, S. Dwarkadas, C. Li, C. Stewart and X. Zhang. Hardware Counter Driven On-the-Fly Request Signatures. In Proc. of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008.
23. J. Skeppstedt and M. Dubois. Hybrid Compiler/Hardware Prefetching for Multiprocessors Using Low-overhead Cache Miss Traps. In Proc. of the International Conference on Parallel Processing, 1997.
24. th International Symposium on Computer Architecture, 2002.
25. th International Symposium on High Performance Computer Architecture, 2007.
26. X.H. Sun, S. Byna and Y. Chen. Improving Data Access Performance with Server Push Architecture. In Proc. of the NSF Next Generation Software Program Workshop in IPDPS'07, 2007.
27. P.F. Sweeney, M. Hauswirth, B. Cahoon, P. Cheng, A. Diwan, D. Grove and M. Hind. Using Hardware Performance Monitors to Understand the Behaviors of Java Applications. In Proc. of the 3rd USENIX Virtual Machine Research and Technology Symp., 2004.
28. S. P. VanderWiel and D. J. Lilja. When Caches Aren't Enough: Data Prefetching Techniques. IEEE Computer, Vol. 30, No. 7, pp.23-30, 1997.
29. W.A. Wulf and S.A. McKee. Hitting the Memory Wall: Implications of the Obvious. In Computer Architecture News, 23(1):20-24, March 1995.
30. X. Zhang, S. Dwarkadas, G. Folkmanis and K. Shen. Processor Hardware Counter Statistics As A First-Class System Resource. In Proc. of the 11th Workshop on Hot Topics in Operating Systems, 2007.
31. th International Conference on Parallel Architectures and Compilation Techniques, 2005.
32. Standard Performance Evaluation Corporation, SPEC Benchmarks, http://www.spec.org/.