SAMS multi-layout memory: Providing multiple views of data to boost SIMD performance

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2010, Pages 179-188

  Gou, Chunyang ^a   Kuzmanov, Georgi ^a   Gaydadjiev, Georgi N ^a  

^a Delft University of Technology ^*  (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; CELL PROCESSOR; CRITICAL PATH DELAYS; DATA REPRESENTATIONS; DYNAMIC INSTRUCTIONS; EXECUTION TIME; EXPERIMENTAL EVALUATION; HARDWARE IMPLEMENTATIONS; HARDWARE OVERHEADS; MEMORY HIERARCHY; MEMORY SYSTEMS; MULTIPLE VIEWS; PARALLEL MEMORY; REAL APPLICATIONS; SAMS; STRUCTURE OF ARRAY; STRUCTURED DATA;

CMOS INTEGRATED CIRCUITS; HARDWARE; INTELLIGENT CONTROL;

NANOTECHNOLOGY;

EID: 77954724842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1810085.1810111     Document Type: Conference Paper

References (32)

1. http://pcsostres.ac.upc.edu/cellsim/doku.php.
2. http://www.ibm.com/developerworks/power/cell/.
3. A. Seznec and R. Espasa. Conflict-free accesses to strided vectors on a banked cache. IEEE Trans. Computers, 54(7):913-916, 2005.
4. M. Alvarez, E. Salami, A. Ramirez, and M. Valero. Performance impact of unaligned memory operations in SIMD extensions for video codec applications. In ISPASS '07: Proceedings of the 2007 International Symposium on Performance Analysis of Systems and Software, pages 62-71, 2007.
5. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: characterization and architectural implications. In PACT '08: Proceedings of the 17th international conference on Parallel Architectures and Compilation Techniques, pages 72-81, 2008.
6. P. Budnik and D. J. Kuck. The organization and use of parallel memories. IEEE Trans. Comput., 20(12):1566-1569, 1971.
7. D. Callahan, K. Kennedy, and A. Porterfield. Software prefetching. In ASPLOS-IV: Proceedings of the fourth international conference on Architectural Support for Programming Languages and Operating Systems, pages 40-52, 1991.
8. J. Carter, W. Hsieh, L. Stoller, M. Swanson, L. Zhang, E. Brunvand, A. Davis, C.-C. Kuo, R. Kuramkote, M. Parker, L. Schaelicke, and T. Tateyama. Impulse: Building a smarter memory controller. In HPCA '99: Proceedings of the 5th international symposium on High Performance Computer Architecture, pages 70-79, 1999.
9. T.-F. Chen and J.-L. Baer. A performance study of software and hardware data prefetching schemes. In ISCA '94: Proceedings of the 21st annual International Symposium on Computer Architecture, pages 223-232, 1994.
10. T. Cheung and J. E. Smith. A simulation study of the CRAY X-MP memory system. IEEE Trans. Comput., 35(7):613-622, 1986.
11. J. Corbal, R. Espasa, and M. Valero. Command vector memory systems: High performance at low cost. In PACT '98: Proceedings of the 1998 international conference on Parallel Architectures and Compilation Techniques, pages 68-77, 1998.
12. Cray Research Inc. Cray Y-MP C90 system programmer reference manual. 1993.
13. D. T. Harper III. Block, multistride vector and FFT accesses in parallel memory systems. IEEE Trans. Parallel and Distributed Systems, 2(1):43-51, 1991.
14. D. T. Harper III. Increased memory performance during vector accesses through the use of linear address transformations. IEEE Trans. Comput., 41(2):227-230, 1992.
15. D. T. Harper III and D. A. Linebarger. Conflict-free vector access using a dynamic storage scheme. IEEE Trans. Comput., 40(3):276-283, 1991.
16. S. Dhong, O. Takahashi, M. White, T. Asano, T. Nakazato, J. Silberman, A. Kawasumi, and H. Yoshihara. A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a Cell processor. In Proceedings of IEEE Int'l Solid-State Circuits Conference 2005, pages 486-612, 2005.
17. B. Flachs, S. Asano, S. Dhong, P. Hotstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty, B. Michael, H. Oh, S. Mueller, O. Takahashi, A. Hatakeyama, Y. Watanabe, and N. Yano. A streaming processing unit for a Cell processor. In Proceedings of IEEE Int'l Solid-State Circuits Conference 2005, pages 134-135, 2005.
18. T. Forsyth. SIMD programming with Larrabee. http://software.intel.com/ file/15545.
19. C. Gou, G. K. Kuzmanov, and G. N. Gaydadjiev. SAMS: Single-Affiliation Multiple-Stride parallel memory scheme. In MAW '08: Proceedings of the 2008 Workshop on Memory Access on future processors, pages 359-367, 2008.
20. IBM Systems and Technology Group. Cell BE programming tutorial v3.0. http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/ FC857AE550F7EB83872571A80061F788.
21. IBM Systems and Technology Group. Developing code for Cell - SIMD. www.cc.gatech.edu/~bader/cell/Day1-06 DevelopingCodeforCell-SIMD.ppt.
22. K. Z. Ibrahim and F. Bodin. Implementing Wilson-Dirac operator on the Cell Broadband Engine. In ICS '08: Proceedings of the 22nd annual International Conference on Supercomputing, pages 4-14, 2008.
23. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy. Introduction to the Cell multiprocessor. IBM J. Res. & Dev., 49(4/5):589-604, 2005.
24. D. Kim, M. Chaudhuri, M. Heinrich, and E. Speight. Architectural support for uniprocessor and multiprocessor active memory systems. IEEE Trans. Comput., 53(3):288-307, 2004.
25. N. Mäding, J. Leenstra, J. Pille, R. Sautter, S. Büttner, S. Ehrenreich, and W. Haller. The vector fixed point unit of the Synergistic Processor Element of the Cell architecture processor. In DATE '06: Proceedings of the conference on Design, Automation and Test in Europe, pages 244-248, 2006.
26. D. Nuzman, I. Rosen, and A. Zaks. Auto-vectorization of interleaved data for SIMD. In PLDI '06: Proceedings of the 2006 conference on Programming Language Design and Implementation, pages 132-143, 2006.
27. D. Nuzman and A. Zaks. Outer-loop vectorization: revisited for short simd architectures. In PACT '08: Proceedings of the 17th international conference on Parallel Architectures and Compilation Techniques, pages 2-11, 2008.
28. W. Oed and O. Lange. On the effective bandwidth of interleaved memories in vector processor systems. IEEE Trans. Comput., 34(10):949-957, 1985.
29. S. Palacharla and R. E. Kessler. Evaluating stream buffers as a secondary cache replacement. In ISCA '94: Proceedings of the 21st annual International Symposium on Computer Architecture, pages 24-33, 1994.
30. D. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. Chaudhry, D. Cox, P. Harvey, H. Harvey, P.M. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Pham, J. Pille, S. Posluszny, M. Riley, D. Stasiak, M. Suzuoki, O. Takahashi, J. Warnock, S. Weitzel, D. Wendel, and K. Yazawa. Overview of the architecture, circuit design, and physical implementation of a first-generation Cell processor. IEEE Journal of Solid-State Circuits, 41:179-196, 2005.
31. G. Ren, P. Wu, and D. Padua. Optimizing data permutations for SIMD devices. In PLDI '06: Proceedings of the 2006 ACM SIGPLAN conference on Programming Language Design and Implementation, pages 118-131, 2006.
32. M. Valero, T. Lang, M. Peiron, and E. Ayguade. Conflict-free access for streams in multimodule memories. IEEE Trans. Comput., 44:634-646, 1995.