Conflict-Free Accesses to Strided Vectors on a Banked Cache

IEEE Transactions on Computers

Volumn 54, Issue 7, 2005, Pages 913-916

  Seznec, Andre ^a   Espasa, Roger ^b  

^a CAMPUS DE BEAULIEU   (France)

^b INTEL CORPORATION   (United States)

Author keywords

conflict free access; L2 caches; strided vectors; Vector microprocessor

Indexed keywords

EID: 85008008151     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.110     Document Type: Article

References (6)

1. P. Budnik and D. Kuck, “The Organization and Use of Parallel Memories,” IEEE Trans. Computers, vol. 20, no. 12, pp. 1566–1569, Dec. 1971.
2. R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec, “Tarantula: A Vector Extension to the Alpha Architecture,” Proc. 29th Int'l Symp. Computer Architecture, May 2002.
3. D. Harper and J. Jump, “Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme,” IEEE Trans. Computers, vol. 36, no. 12, pp. 1440–1449, Dec. 1987.
4. D.H. Lawrie and C.R. Vora, “The Prime Memory System for Array Access,” IEEE Trans. Computers, vol. 31, no. 5, pp. 435–442, May 1982.
5. M. Peiron, M. Valero, E. Ayguade, and T. Lang, “Vector Multiprocessors with Arbitrated Memory Access,” Proc. 22nd Ann. Int'l Symp. Computer Architecture, June 1995.
6. A. Seznec and J. Lenfant, “Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers,” Proc. 19th Ann. Int'l Symp. Computer Architecture, May 1992.