Energy-efficient redundant execution for chip multiprocessors

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 143-146

  Subramanyan, Pramod ^a   Singh, Virendra ^a   Saluja, Kewal K ^b   Larsson, Erik ^c  

^a INDIAN INSTITUTE OF SCIENCE   (India)

^b University of Wisconsin Madison   (United States)

^c LINKÖPING UNIVERSITY   (Sweden)

Author keywords

microarchitecture; permanent faults; redundant execution; transient faults

Indexed keywords

CHIP MULTIPROCESSOR; CMOS SCALING; CORE DYNAMICS; DESIGN TOLERANCES; ENERGY EFFICIENT; FAULT-TOLERANT; MICRO ARCHITECTURES; ON CHIPS; ON-CHIP MULTIPROCESSOR; PERMANENT FAULTS; POWER EFFICIENT; TRANSIENT FAULTS;

FITS AND TOLERANCES; LAKES; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE;

FAULT TOLERANCE;

EID: 77954513706     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785516     Document Type: Conference Paper

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