A 500 mW ADC-Based CMOS AFE with digital calibration for 10 gb/s serial links over kr-backplane and multimode fiber

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 6, 2010, Pages 1172-1185

  Cao, Jun ^a   Zhang, Bo ^a   Singh, Ullas ^a   Cui, Delong ^a   Vasani, Anand ^a   Garg, Adesh ^a   Zhang, Wei ^a   Kocaman, Namik ^a   Pi, Deyi ^a   Raghavan, Bharath ^a   Pan, Hui ^a   Fujimori, Ichiro ^a   Momtaz, Afshin ^a  

^a BROADCOM CORPORATION   (United States)

Author keywords

Adaptive equalization; Backplane; Calibration; De emphasis; DSP based transceiver; EDC; Gain mismatch; KR; LC VCO; LRM; Multimode; Optical fiber; PGA; Phase mismatch; Phase locked loop; PLL; Time interleaved ADC; Tuned buffers

Indexed keywords

ADAPTIVE EQUALIZATION; BACKPLANE; BACKPLANES; DE-EMPHASIS; DSP-BASED; GAIN MISMATCH; MULTIMODE OPTICAL FIBERS; PHASE MISMATCH; TIME-INTERLEAVED ADC;

CALIBRATION; CMOS INTEGRATED CIRCUITS; DIFFERENTIAL AMPLIFIERS; DIGITAL SIGNAL PROCESSORS; FIBERS; JITTER; MULTIMODE FIBERS; OPTICAL FIBERS; PROGRAMMED CONTROL SYSTEMS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

PHASE LOCKED LOOPS;

EID: 77953261789     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2047473     Document Type: Article

References (27)

1. Ethernet Operation Over Electrical Backplanes, IEEE Std 802.3ap- 2007, May 2007.
2. Physical Layer and Management Parameters for 10 Gb/s Operation, Type 10 GBASE-LRM, IEEE Std 802.3aq-2006, Oct. 2006.
3. H. Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. Chopra, "An MLSE receiver for electronic dispersion compensation of OC-192 fiber links," IEEE J. Solid-State Circuits, vol.41, no.11, pp. 2541-2554, Nov. 2006.
4. M. Harwood, N. Warke, R. Simpson, T. Leslie, A. Amerasekera, S. Batty, D. Colman, E. Carr, V. Gopinathan, S. Hubbins, P. Hunt, A. Joy, P. Khandelwal, B. Killips, T. Krause, S. Lytollis, A. Pickering, M. Saxton, D. Sebastio, G. Swanson, A. Szczepanek, T.Ward, J.Williams, R. Williams, and T. Willwerth, "A 12.5 Gb/s serdes in 65 nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 436-437.
5. O. Agazzi, D. Crivelli, M. Hueda, H. Carrer, G. Luna, A. Nazemi, C. Grace, B. Kobeissy, C. Abidin, M. Kazemi, M. Kargar, C. Marquez, S. Ramprasad, F. Bollo, V. Posse, S. Wang, G. Asmanis, G. Eaton, N. Swenson, T. Lindsay, and P. Voois, "A 90 nm CMOS DSP MLSD transceiver with integrated AFE for electronic dispersion compensation of multimode optical fibers at 10 Gb/s," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 2939-2957, Apr. 2008.
6. K. Azadet, E. F. Haratsch, H. Kim, F. Saibi, J. H. Saunders, M. Shaffer, L. Song, and M. Yu, "Equalization and FEC techniques for optical transceivers," IEEE J. Solid-State Circuits, vol.37, no.3, pp. 317-327, Mar. 2002.
7. J. Cao, B. Zhang, U. Singh, D. Cui, A. Vasani, A. Garg, W. Zhang, N. Kocaman, D. Pi, B. Raghavan, H. Pan, I. Fujimori, and A. Momtaz, "A 500 mW digitally calibrated AFE in 65 nm CMOS for 10 Gb/s serial links over backplane and multimode fiber," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 370-371.
8. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.
9. J. Cao, M. Green, A. Momtaz, K. Vakilian, FD. Chung, K-C Jen, M. Caresosa, X.Wang, W.-G. Tan, Y. Cai, I. Fujimori, and A. Hairapetian, "Transmitter and receiver in standard 0.18 μm CMOS," IEEE J. Solid- State Circuits, vol.37, no.12, pp. 1768-1780, Dec. 2002.
10. W. C. Black, Jr and D. A. Hodges, "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol.SC-15, no.6, pp. 1022-1029, Dec. 1980.
11. A. Nazemi, C. Grace, L. Lewyn, B. Kobeissy, O. Agazzi, P. Voois, C. Abidin, G. Eaton, M. Kargar, C. Marquez, S. Ramprasad, F. Bollo, V. Posse, S. Wang, and G. Asmanis, "A 10.3 GS/s 6 bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 18-19.
12. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 318-319.
13. P. Schvan, J. Bach, C. Falt, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex, J. Sitch, S.-C.Wang, and J.Wolczanski, "A 24 GS/s 6 b ADC in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 544-545.
14. Y.-C. Jenq, "Digital spectra of nonuniformly sampled signals: Fundamentals and high-speed waveform digitizers," IEEE Trans. Instrum. Meas., vol.37, pp. 245-251, Jun. 1988.
15. N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, "Explicit analysis of channel mismatch effects in time interleaved ADC systems," IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol.48, no.3, pp. 261-271, Mar. 2001. (Pubitemid 32394176)
16. C. Vogel, "The impact of combined channel mismatch effects in timeinterleaved ADCs," IEEE Trans. Instrum. Meas., vol.54, no.1, pp. 415-427, Feb. 2005.
17. D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, "A digital background calibration technique for time-interleaved analog-to-digital converters," IEEE J. Solid-State Circuits, vol.33, no.12, pp. 1904-1911, Dec. 1998. (Pubitemid 128568588)
18. S. M. Louwsma, A. J. M. van Tuijl, M. Vertregt, and B. Nauta, "A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 778-786, Apr. 2008.
19. S. K. Gupta, M. A. Inerfield, and J.Wang, "A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture," IEEE J. Solid-State Circuits, vol.41, no.3, pp. 2650-2657, Mar. 2009.
20. B. Razavi and B. A.Wooley, "Design techniques for high-speed, highresolution comparators," IEEE J .Solid-State Circuits, vol.27, no.12, pp. 1916-1926, Dec. 1992.
21. G. M. Yin, F. O. Eynde, and W. Sansen, "A high-speed CMOS comparator with 8-b resolution," IEEE J. Solid-State Circuits, vol.27, no.2, pp. 208-211, Feb. 1992.
22. T. Beukema, M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, B. Parker, and M. Beakes, "A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2633-2645, Dec. 2005.
23. M. Meghelli, S. Rylov, J. Bulzacchelli, W. Rhee, A. Rylyakov, H. Ainspan, B. Parker, M. Beakes, A. Chung, T. Beukema, P. Pepeljugoski, L. Shan, Y. Kwark, S. Gowda, and D. Friedman, "A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 80-81.
24. A. Kral, F. Behbahani, and A. A. Abidi, "RF-CMOS oscillators with switched tuning," in Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 555-558.
25. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998, ch. 4.
26. S. Shahramian, S. P. Voinigescu, and A. C. Carusone, "A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees," IEEE J. Solid-State Circuits, vol.44, no.6, pp. 1709-1720, Jun. 2009.
27. SFF-8431 Specifications for Enhanced Small Form Factor Pluggable Module SFP+, Revision 4.0, SFF Committee, 2009.