-
1
-
-
0006219588
-
300 pin multi source agreement for 10 gigabit transponders (serdes transceivers)
-
Apr.
-
"300 pin multi source agreement for 10 gigabit transponders (serdes transceivers)," in 10 Giga MSA Consortium, Apr. 2001.
-
(2001)
10 Giga MSA Consortium
-
-
-
3
-
-
0012156481
-
-
SONET OC-192, Bellcore, GR-1377-CORE no. 4, Mar.
-
SONET OC-192, "Transport system generic criteria," Bellcore, GR-1377-CORE no. 4, Mar. 1998.
-
(1998)
Transport system generic criteria
-
-
-
4
-
-
0036105959
-
OC-192 receiver in standard 0.18 μm CMOS
-
Feb.
-
J. Cao, A. Momtaz, K. Vakilian, M. Green, D. Chung, K. Jen, M. Caresosa, B. Tan, I. Fujimori, and A. Hairapetian, "OC-192 receiver in standard 0.18 μm CMOS," in ISSCC 2002 Dig. Tech. Papers, Feb. 2002, pp. 250-251.
-
(2002)
ISSCC 2002 Dig. Tech. Papers
, pp. 250-251
-
-
Cao, J.1
Momtaz, A.2
Vakilian, K.3
Green, M.4
Chung, D.5
Jen, K.6
Caresosa, M.7
Tan, B.8
Fujimori, I.9
Hairapetian, A.10
-
6
-
-
0035054818
-
A 10 Gb/s CMOS clock and data recovery circuit with frequency detection
-
Feb.
-
J. Savoj and B. Razavi, A 10 Gb/s CMOS clock data recovery circuit with frequency detection, " in ISSCC 2001 Dig. Tech. Papers, Feb. 2001, pp. 78-79.
-
(2001)
ISSCC 2001 Dig. Tech. Papers
, pp. 78-79
-
-
Savoj, J.1
Razavi, B.2
-
7
-
-
0034476465
-
A fully integrated SiGe receiver IC for 10-Gb/s data rate
-
Dec.
-
Y. Greshishchev, P. Schvan, J.L. Showell, M.-L. Xu, J.J. Ojha, and J.E. Roger, "A fully integrated SiGe receiver IC for 10-Gb/s data rate," IEEE J. Solid-State Circuits, vol. 35, pp. 1949-1957, Dec. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1949-1957
-
-
Greshishchev, Y.1
Schvan, P.2
Showell, J.L.3
Xu, M.-L.4
Ojha, J.J.5
Roger, J.E.6
-
8
-
-
0026996358
-
A 155-MHz clock recovery delay-and phase-locked loop
-
Dec.
-
T.H. Lee and J.F. Bulzacchelli, "A 155-MHz clock recovery delay-and phase-locked loop," IEEE J. Solid-State Circuits, vol. 27, pp. 1736-1746, Dec. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1736-1746
-
-
Lee, T.H.1
Bulzacchelli, J.F.2
-
10
-
-
0016565959
-
Clock recovery from random binary signals
-
Oct.
-
J.J.D.H. Alexander, "Clock recovery from random binary signals," Electron.. Lett., vol. 11, pp. 541-542, Oct. 1975.
-
(1975)
Electron.. Lett.
, vol.11
, pp. 541-542
-
-
Alexander, J.J.D.H.1
-
11
-
-
6444245805
-
Fully-integrated SONET OC48 transceiver in standard CMOS
-
Dec.
-
A. Momtaz, J. Cao, M. Caresosa, A. Hairapetian, D. Chung, K. Vakilian, M. Green, B. Tan, K. Jen, I. Fujimori, and Y. Cai, "Fully-integrated SONET OC48 transceiver in standard CMOS," IEEE J. Solid-State Circuits, vol. 25, pp. 1964-1973, Dec. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.25
, pp. 1964-1973
-
-
Momtaz, A.1
Cao, J.2
Caresosa, M.3
Hairapetian, A.4
Chung, D.5
Vakilian, K.6
Green, M.7
Tan, B.8
Jen, K.9
Fujimori, I.10
Cai, Y.11
-
12
-
-
0004097131
-
IEEE standard for low-voltage differential signals (LVDS) for scalable coherent interface (SCI)
-
Mar.
-
IEEE Standard for low-voltage differential signals (LVDS) for scalable coherent interface (SCI), IEEE Std. 1596.3-1996, Mar. 1996.
-
(1996)
IEEE Std. 1596.3 - 1996
-
-
-
13
-
-
84938174380
-
A simple model of feedback osciliator noise spectrum
-
Feb.
-
D.B. Leeson, "A simple model of feedback osciliator noise spectrum," Proc. IEEE, pp. 329-330, Feb. 1966.
-
(1966)
Proc. IEEE
, pp. 329-330
-
-
Leeson, D.B.1
-
14
-
-
0032120045
-
Spectrum folding and phase noise in LC tuned oscillators
-
July
-
C. Samori, A.L. Lacaita, F. Villa, and F. Zappa, "Spectrum folding and phase noise in LC tuned oscillators," IEEE Trans. Circuits Syst. II, vol. 45, pp. 781-790, July 1998.
-
(1998)
IEEE Trans. Circuits Syst. II
, vol.45
, pp. 781-790
-
-
Samori, C.1
Lacaita, A.L.2
Villa, F.3
Zappa, F.4
-
15
-
-
0032635507
-
Design issues in CMOS differential LC oscillators
-
May
-
A. Hajimiri and T.H. Lee, "Design issues in CMOS differential LC oscillators," IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 717-724
-
-
Hajimiri, A.1
Lee, T.H.2
-
16
-
-
0032002580
-
A general theory of phase noise in electrical oscillators
-
Oct.
-
_, "A general theory of phase noise in electrical oscillators," IEEE J. Solid-State Circuits, vol. 33, pp. 1218-1223, Oct. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 1218-1223
-
-
-
17
-
-
0035054908
-
A 2.75 Gb/s CMOS clock recovery circuit with broad capture range
-
Feb.
-
S.B. Anand and B. Razavi, "A 2.75Gb/s CMOS clock recovery circuit with broad capture range," in ISSCC 2001 Dig. Tech. Papers, Feb. 2001, pp. 78-79.
-
(2001)
ISSCC 2001 Dig. Tech. Papers
, pp. 78-79
-
-
Anand, S.B.1
Razavi, B.2
-
18
-
-
0036106115
-
OC-192 transmitter in standard 0.18 μm CMOS
-
Feb.
-
M. Green, A. Momtaz, K. Vakilian, X. Wang, K. Jen, D. Chung, J. Cao, M. Caresosa, A. Hairapetian, I. Fujimori, and Y. Cai, "OC-192 transmitter in standard 0.18 μm CMOS," in ISSCC 2002 Dig. Tech. Papers, Feb. 2002, pp. 248-249.
-
(2002)
ISSCC 2002 Dig. Tech. Papers
, pp. 248-249
-
-
Green, M.1
Momtaz, A.2
Vakilian, K.3
Wang, X.4
Jen, K.5
Chung, D.6
Cao, J.7
Caresosa, M.8
Hairapetian, A.9
Fujimori, I.10
Cai, Y.11
-
19
-
-
0035693579
-
A 10-Gb/s 16 : 1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS
-
Dec.
-
H. Cong, S.M. Logan, M.J. Loinaz, K.J. O'Brien, E.E. Perry, G.D. Polhemus, J.E. Scoggins, K.P. Snowdon, and M.G. Ward, "A 10-Gb/s 16 : 1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1946-1953, Dec. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1946-1953
-
-
Cong, H.1
Logan, S.M.2
Loinaz, M.J.3
O'Brien, K.J.4
Perry, E.E.5
Polhemus, G.D.6
Scoggins, J.E.7
Snowdon, K.P.8
Ward, M.G.9
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