Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics

Microelectronics Reliability

Volumn 50, Issue 6, 2010, Pages 790-793

  Kakushima, K ^a   Tachi, K ^a   Ahmet, P ^a   Tsutsui, K ^a   Sugii, N ^a   Hattori, T ^a   Iwai, H ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE PERFORMANCE; EQUIVALENT OXIDE THICKNESS; GATE ELECTRODES; GATE OXIDE; INVERSION LAYER; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; MOS-FET; PARASITIC CAPACITANCE; SATURATION REGION;

DIELECTRIC MATERIALS; DRAIN CURRENT; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); MOS DEVICES; MOSFET DEVICES;

GATE DIELECTRICS;

EID: 77953130564     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.02.001     Document Type: Article

References (13)

1. Iwai H. CMOS technology-year 2010 and beyond. IEEE J Solid-State Circ 34 3 (1999) 357-366
2. 2 to high-k. In: Extended abstracts of international workshop on gate insulator; 2003. p. 124-6.
3. Wilk G.D., Wallace R.M., and Anthony J.M. High-k gate dielectrics: current status, materials properties considerations. J Appl Phys 89 (2001) 5243
4. Suzuki M, Tomita M, Yamaguchi T, Fukushima N. Ultra-thin (EOT = 3A) and low leakage dielectric of La-aluminate directly on Si substrate fabricated by high temperature deposition. In: Tech dig of int'l electron dev meeting; 2005. p. 445-8.
5. Takagi S., Takayanagi M., and Toriumi A. Characterization of inversion-layer capacitance of holes in Si MOSFET's. IEEE Trans Electron Dev 46 7 (1999) 1446-1450
6. Black C.T., and Welser J.J. Electric-field penetration into metals: consequences for high-dielectric-constant capacitors. IEEE Trans Electron Dev 46 4 (1999) 776-780
7. Natori K, Oniki M, Kurusu T, Shimizu T. Capacitance due to the charge layer thickness in nanoscale capacitors. In: Extended abstracts of the 2005 int'l conference on solid state device and materials; 2005. p. 286-7.
8. http://www.itrs.net/.
9. Hauser J. CVC 2000 NCSU software, version 5.0., Raleigh, USA: Department of Electrical and Computer Engineering, North Carolina State University.
10. Takagi S., and Takayanagi M. Experimental evidence of inversion-layer mobility lowering in ultrathin gate oxide metal-oxide-semiconductor field-effect-transistors with direct tunneling current. Jpn J Appl Phys 41 (2002) 2348-2352
11. 2 gate stacks. J Appl Phys 98 (2005) 113706
12. Momose S.H., Ono M., Yoshitomi T., Ohguro T., Nakamura S., Saito M., et al. 1.5 nm direct-tunneling gate oxide Si MOSFET's. IEEE Trans Electron Dev 43 8 (1996) 1233-1242
13. 3 film deposition. ECS Trans 3 3 (2006) 425-434