Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

IET Computers and Digital Techniques

Volumn 3, Issue 5, 2009, Pages 487-500

  Tran, X T ^a,c   Thonnart, Y ^a   Durupt, J ^a   Beroulle, V ^b   Robach, C ^b  

^a CEA LETI   (France)

^b Grenoble Institute of Technology   (France)

^c VIETNAM NATIONAL UNIVERSITY   (Viet Nam)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS DESIGN; ASYNCHRONOUS NETWORKS; ATTRACTIVE SOLUTIONS; AUTOMATICALLY GENERATED; DESIGN FOR TEST; FAULT COVERAGES; NETWORK ROUTERS; NETWORK SIZE; NETWORK TOPOLOGY; NETWORKS ON CHIPS; NOC ARCHITECTURES; POST-FABRICATION; SIMPLE METHOD; SINGLE STUCK-AT FAULTS; TEST PATTERN; TEST PATTERN GENERATIONS; TESTABILITY; TESTING METHODOLOGY; TESTING STRATEGIES; TIMING CONSTRAINTS;

ARCHITECTURAL DESIGN; AUTOMATIC TEST PATTERN GENERATION; ELECTRIC NETWORK TOPOLOGY; TESTING; TIMING CIRCUITS;

ROUTERS;

EID: 68849097905     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0072     Document Type: Article

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