An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2009, Pages 141-147

  Shelar, Rupesh S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Clock distribution; Low power; Routing

Indexed keywords

45NM TECHNOLOGY; CLOCK DISTRIBUTION; CLOCK GRID; EFFICIENT ALGORITHM; ENTIRE DIE; GRID OVERLAYS; HYBRID NETWORK; LOW POWER; MODERN MICROPROCESSOR; ROUTING; SPECIFIC LOCATION; WIRE LENGTH; WIRELENGTH MINIMIZATION;

CAPACITANCE; ELECTRIC CLOCKS; HEURISTIC ALGORITHMS; MICROPROCESSOR CHIPS; WIRE;

ROUTING ALGORITHMS;

EID: 70349150933     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1514932.1514964     Document Type: Conference Paper

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