Predictability of load/store instruction latencies

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 1994, Pages 139-152

  Abraham, Santosh G ^a   Sugumar, Rabin A ^a   Windheiser, Daniel ^a   Rau, B R ^a   Gupta, Rajiv ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED INSTRUCTION; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; OPTIMIZATION; PERFORMANCE; PROGRAM COMPILERS; REDUCED INSTRUCTION SET COMPUTING; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING;

CACHE CONTROL INSTRUCTION; CACHE MISS LATENCIES; LOAD/STORE INSTRUCTION LATENCIES; MEMORY REFERENCING BEHAVIOR; MISS RATIO; PREDICTABILITY;

PROGRAM PROCESSORS;

EID: 0028055525     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)