Managing data caches using selective cache line replacement

International Journal of Parallel Programming

Volumn 25, Issue 3, 1997, Pages 213-242

  Tyson, Gary ^a   Farrens, Matthew ^b   Matthews, John ^b   Pleszkun, Andrew R ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b University of California   (United States)

^c UCB 450   (United States)

Author keywords

Belady; Cache replacement policy; Dynamic reference behavior; Memory management; Optimal placement strategies

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DYNAMIC PROGRAMMING; RESOURCE ALLOCATION; STORAGE ALLOCATION (COMPUTER);

CACHE REPLACEMENT POLICY; DATA CACHES; INDIVIDUAL LOAD INSTRUCTIONS;

BUFFER STORAGE;

EID: 0031164362     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF02700036     Document Type: Article

References (19)

1. J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufman, San Mateo, California (1990).
2. J. M. Mulder, N. T. Quach, and M. J. Flynn, An Area Model for On-Chip Memories and Its Application, IEEE J. Solid-State Circuits, 26(2):98-105 (February 1991).
3. T. Wada, S. Rajan, and S. A. Przybylski, An Analytical Access Time Model for On-Chip Cache Memories, IEEE J. Solid-State Circuits, 27(8):1147-1156 (August 1992).
4. D. Callahan and A. Porterfield, Data Cache Performance and Supercomputer Applications, Proc. Supercomputing, pp. 564-572 (1990).
5. A. C. Klaiber and H. M. Levy, An Architecture for Software-Controlled Data Prefetching, Proc. 18th Ann. Int'l. Symp. Computer Archit., Toronto, Canada, pp. 43-53 (May 1991).
6. T. Chen and J. Baer, Effective Hardware Based Data Prefetching for High-Performance Processors, IEEE Trans. Computers 44(5):609-623 (May 1995).
7. P. G. Emma, J. W. Knight, J. H. Pomerene, T. R. Puzak, and R. N. Rechtschaffen, Cache Miss Facility with Stored Sequences for Data Fetching, U.S. Patent 5, 233, 702 (I: August 3, 1993).
8. N. Jouppi, Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. 17th Ann. Int'l. Symp. Archit. 18(2):364-373 (May 1990).
9. S. G. Abraham, R. A. Sugumar, D. Windheiser, B. R. Rau, and R. Gupta, Predictability of Load/Store Instruction Latencies, Proc. 26th Ann. Int'l. Symp. Microarchitecture, Austin, Texas, pp. 139-152 (December 1993).
10. A. Srivastava and A. Eustace, ATOM: A System for Building Customized Program Analysis Tools, Proc. ACM SIGPLAN Notices Conf. Progr. Lang. Implementations, pp. 196-205 (June 1994).
11. J. E. Smith, A Study of Branch Prediction Strategies, Proc. Eighth Ann. Int'l. Symp. Computer Archit., Minneapolis, Minnesota, pp. 135-148 (May 1981).
12. B. Calder and D. Grunwald, Fast and Accurate Instruction Fetch and Branch Prediction, ISCA21, Chicago, Illinois, pp. 2-11 (April 18-21, 1994).
13. T. Yeh and Y. Patt, A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History, Proc. 20th Ann. Int'l. Symp. Computer Archit., San Diego, California, pp. 257-266 (May 1993).
14. J. A. Fisher and S. M. Freudenberger, Predicting Conditional Branch Directions from Previous Runs of a Program, Proc. Fifth Int'l. Conf. Archit. Support for Progr. Lang. and Oper. Syst., Boston, Massachusetts, pp. 85-95 (October, 1992).
15. T. Yeh and Y. Patt, Alternative Implementations of Two-Level Adaptive Training Branch Prediction, Proc. 19th Ann. Int'l. Symp. Computer Archit., Queensland, Australia, pp. 124-134 (May, 1992).
16. S. Pan, K. So and J. T. Rahmeh, Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation, Proc. Fifth Int'l. Conf. Archit. Support for Progr. Lang. and Oper. Syst., Boston, Massachusetts, pp. 76-84 (October, 1992).
17. T. Yeh and Y. Patt, Two-Level Adaptive Training Branch Prediction, Proc. 24th Ann. Int'l. Symp. Microarchitecture, Albuquerque, New Mexico, pp. 51-61 (November, 1991).
18. P. Chang, E. Hao, T. Yeh, and Y. Patt, Branch Classification: A New Mechanism for Improving Branch Predictor Performance, Proc. 27th Ann. Int'l. Symp. Microarchitecture, San Jose, California, pp. 22-31 (November 30-December 2, 1994).
19. L. A. Belady, A Study of Replacement Algorithms for a Virtual-Storage Computer, IBM Syst. J. 5(2):282-288 (1966).