Energy-delay analysis for on-chip interconnect at the system level

Proceedings - IEEE Computer Society Workshop on VLSI 1999: System Design: Towards System-on-a-Chip Paradigm, VLSI 1999

Volumn , Issue , 1999, Pages 26-31

  Zhang, Yan ^a   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SIGNAL PROCESSING; VLSI CIRCUITS;

ARCHITECTURAL LEVELS; COMMERCIAL CHIPS; DEEP SUB-MICRON TECHNOLOGY; ENERGY-DELAY ANALYSIS; INTERCONNECT POWER; ON CHIP INTERCONNECT; SYNTHETIC BENCHMARK; TOTAL CHIP AREA;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84943153769     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.1999.760465     Document Type: Conference Paper

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