Combined DRAM and logic chip for massively parallel systems

Proceedings - 16th Conference on Advanced Research in VLSI, ARVLSI 1995

Volumn , Issue , 1995, Pages 4-16

  Kogge, P M ^a   Sunaga, T ^b   Miyataka, H ^b   Kitamura, K ^b   Retter, E ^c  

^a UNIVERSITY OF NOTRE DAME   (United States)

^b IBM JAPAN LTD   (Japan)

^c LOCKHEED MARTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; DYNAMIC RANDOM ACCESS STORAGE; MACROS; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

CHIP TECHNOLOGY; CMOS TECHNOLOGY; CUSTOM CIRCUITS; HIGH DENSITY MEMORY; MASSIVELY PARALLEL PROCESSING; MASSIVELY PARALLEL SYSTEMS; PROCESSOR-IN-MEMORY; SINGLE PARTS;

COMPUTER CIRCUITS;

EID: 84870766462     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1995.515607     Document Type: Conference Paper

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