Implementation of 4-bit reversible parallel adder using nanoelectronic single-electron circuitry

Journal of Nanoelectronics and Optoelectronics

Volumn 4, Issue 3, 2009, Pages 362-369

  Singh, C J Clement ^a   Sarkar, Subir Kumar ^a   Biswas, Anup Kumar ^b  

^a JADAVPUR UNIVERSITY   (India)

^b Jalpaiguri Goverment Engineering College   (India)

Author keywords

Coulomb island; Power efficient; Single electron device; Single electron tunneling (SET); Single electron circuit

Indexed keywords

ARITHMETIC FUNCTIONS; DEVICE SIZES; GATE VOLTAGES; HIGH DENSITY; LOW POWER; MOSFETS; PARALLEL ADDERS; POWER CONSUMPTION; POWER EFFICIENT; SIMULATED MODEL; SINGLE ELECTRON; SINGLE ELECTRON TECHNOLOGY; SINGLE-ELECTRON CIRCUITS; SINGLE-ELECTRON DEVICES; SINGLE-ELECTRON LOGIC; SINGLE-ELECTRON TUNNELING;

COMPUTER SIMULATION; ELECTRON DEVICES; ELECTRON TUNNELING; ELECTRONS; LOGIC CIRCUITS; LOGIC DESIGN; NUMBER THEORY; STATIC RANDOM ACCESS STORAGE; SWITCHING CIRCUITS; TRANSIENTS; TUNNELING (EXCAVATION); VLSI CIRCUITS;

SINGLE ELECTRON TRANSISTORS;

EID: 77952698552     PISSN: 1555130X     EISSN: None     Source Type: Journal    
DOI: 10.1166/jno.2009.1052     Document Type: Article

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