Body bias driven design synthesis for optimum performance per area

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 472-477

  Meijer, Maurice ^a   Pineda De Gyvez, Jose ^a,b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Area; Body biasing; CMOS; Logic synthesis; Performance

Indexed keywords

AREA RATIOS; BENCHMARK CIRCUIT; BODY BIAS; BODY BIASING; CIRCUIT PERFORMANCE; CMOS LOGIC; DESIGN SYNTHESIS; DIGITAL CMOS; DYNAMIC POWER; FORWARD BODY BIASING; LEAKAGE REDUCTION; NEW DESIGN; OPTIMUM PERFORMANCE; PERFORMANCE PENALTIES; TOTAL POWER;

CMOS INTEGRATED CIRCUITS; SYNTHESIS (CHEMICAL);

DESIGN;

EID: 77952611746     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450531     Document Type: Conference Paper

References (11)

1. J. Zhang, "Worst Case Design of Digital Integrated Circuits," Proc. of ISCAS, London, UK, June 1994, pp.153-156.
2. S. Duvall, "A Practical Methodology for the Statistical Design of Complex Logic Products for Performance," IEEE Trans. on VLSI Systems, Vol.3, No.1, March 1995, pp.112-123.
3. A.Nardi et al., " Impact of Unrealistic Worst Case Modeling on the Performance of VLSI Circuits in Deep Submicron CMOS Technologies," IEEE Trans. on Semiconductor Manufacturing, Vol.12, No.4, November 1999, pp.396-403.
4. M. Meijer, and J. Pineda de Gyvez, "Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning," in Adaptive Techniques for Dynamic Processor Optimization, A. Wang and S. Naffziger Ed., Springer, 2008, pp.25-47.
5. J. Tschanz et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," Proc. of ISSCC, San Francisco, CA, USA, February 2002, pp.344-345.
6. M. Mani et al., "Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization," Proc. of ICCAD, San Jose, CA, USA, November 2006, pp.19-26.
7. S. Kulkarni et al., "A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering," Proc. of ICCAD, San Jose, CA, USA, Nov.2006, pp.39-46.
8. R. Teodorescu et al., "Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing," Proc. of MICRO-40, Chicago, IL, USA, Dec.2007, pp.27-39.
9. A. Sathanur et al., "Physically Clustered Forward Body Biasing for Variability Compensation in Nanometer CMOS design," Proc. of DATE, Nice, France, April 2009, pp.154-159.
10. M. Hirabayashi et al., "Design Methodology and Optimization Strategy for Dual-VTH Scheme using Commercially Available Tools," Proc. of ISLPED, Huntington Beach, CA, USA, Aug. 2001, pp.283-286.
11. ITC99 benchmarks: www.cad.polito.it/tools/itc99.html