Design methodology and optimization strategy for dual-VTH scheme using commercially available tools

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 283-286

  Hirabayashi, M ^a   Nose, K ^a   Sakurai, T ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; LOGIC DESIGN; LOGIC GATES; MOSFET DEVICES; OPTIMIZATION; THRESHOLD VOLTAGE;

POWER CONSUMPTION;

VLSI CIRCUITS;

EID: 0034878753     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383169     Document Type: Conference Paper

References (7)

1. 1-V power supply high-speed digital circuits technology with multithreshold-voltage CMOS
2. A 0.9-V, 150-MHz 10-mW 4mm2 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
3. Static power optimization of deep submicron CMOS circuits for dual vt technology
4. TH for low-power and high-speed applications