Worst case design of digital integrated circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1994, Pages 153-156

  Zhang, J C ^a  

^a BAKER HUGHES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC CURRENT MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; RANDOM PROCESSES; STATISTICAL METHODS; TRANSISTORS;

VARIABILITY MINIMIZATION; WORST CASE DESIGN;

DIGITAL INTEGRATED CIRCUITS;

EID: 0028591369     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)