Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies

IEEE Transactions on Semiconductor Manufacturing

Volumn 12, Issue 4, 1999, Pages 396-402

  Nardi, Alessandra ^a,b   Neviani, Andrea ^b   Zanoni, Enrico ^a,b   Quarantelli, Michele ^c   Guardiani, Carlo ^a,d  

^a IEEE

^b UNIVERSITY OF PADOVA   (Italy)

^c UNIVERSITY OF BRESCIA   (Italy)

^d PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; PROBABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; STATISTICAL METHODS;

ASSIGNED PROBABILITY TECHNIQUES (APT); WORST CASE MODELS;

VLSI CIRCUITS;

EID: 0033322279     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.806116     Document Type: Article

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