Physically clustered forward body biasing for variability compensation in nanometer CMOS design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 154-159

  Sathanur, Ashoka ^a   Pullini, Antonio ^a   Benini, Luca ^b   De Micheli, Giovanni ^a   Macii, Enrico ^c  

^a EPFL   (Switzerland)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; CMOS INTEGRATED CIRCUITS; HEURISTIC ALGORITHMS; THRESHOLD VOLTAGE; TUNING;

ADAPTIVE BODY BIAS; FORWARD BODY BIAS; FORWARD BODY BIASING; FULLY COMPATIBLE; PHYSICAL DESIGN; POST-FABRICATION; STATE OF THE ART; VARIABILITY COMPENSATION;

INTEGRATED CIRCUIT DESIGN;

EID: 70549106166     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090650     Document Type: Conference Paper

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