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Volumn 58, Issue 5 PART 2, 2010, Pages 1339-1348

A digital frequency synthesizer for cognitive radio spectrum sensing applications

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE AREA; CMOS PROCESSS; COGNITIVE RADIO; DIGITAL FREQUENCY SYNTHESIZER; FREQUENCY RANGES; FREQUENCY RESOLUTIONS; FUNDAMENTAL LIMITATIONS; HIGH FREQUENCY RESOLUTION; LOW POWER; OPERATIONAL BANDWIDTH; POWER CONSUMPTION; SETTLING TIME; SPECTRUM SENSING; WIDE-BAND;

EID: 77952429544     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2010.2042859     Document Type: Conference Paper
Times cited : (20)

References (16)
  • 1
    • 13844296408 scopus 로고    scopus 로고
    • Cognitive radio: Brain-empowered wireless communications
    • Feb.
    • S. Haykin, "Cognitive radio: Brain-empowered wireless communications," IEEE J. Sel. Areas Commun., vol.23, no.2, pp. 201-220, Feb. 2005.
    • (2005) IEEE J. Sel. Areas Commun. , vol.23 , Issue.2 , pp. 201-220
    • Haykin, S.1
  • 2
    • 51349134614 scopus 로고    scopus 로고
    • Spectrum sensing in cognitive radios based on multiple cyclic frequencies
    • J. Lunden, V. Koivunen, A. Huttunent, and H. V. Poort, "Spectrum sensing in cognitive radios based on multiple cyclic frequencies," in Proc. CrownCom, Aug. 2007, pp. 37-43.
    • (2007) Proc. CrownCom Aug. , pp. 37-43
    • Lunden, J.1    Koivunen, V.2    Huttunent, A.3    Poort, H.V.4
  • 4
    • 0033703262 scopus 로고    scopus 로고
    • An architecture of high-performance frequency and phase synthesis
    • Jun
    • H. Mair and L. Xiu, "An architecture of high-performance frequency and phase synthesis," IEEE J. Solid-State Circuits, vol.35, no.6, pp. 835-846, Jun. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.6 , pp. 835-846
    • Mair, H.1    Xiu, L.2
  • 5
    • 0036683873 scopus 로고    scopus 로고
    • A direct digital period synthesis circuit
    • Aug.
    • D. E. Calbaza and Y. Savaria, "A direct digital period synthesis circuit," IEEE J. Solid-State Circuits, vol.37, no.8, pp. 1039-1045, Aug. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.8 , pp. 1039-1045
    • Calbaza, D.E.1    Savaria, Y.2
  • 6
    • 0037456484 scopus 로고    scopus 로고
    • Multimode clock generation using delay-locked loop
    • Feb.
    • O. Susplugas and P. Philippe, "Multimode clock generation using delay-locked loop," Electron. Lett., vol.39, no.4, pp. 347-349, Feb. 2003.
    • (2003) Electron. Lett. , vol.39 , Issue.4 , pp. 347-349
    • Susplugas, O.1    Philippe, P.2
  • 7
    • 70350228513 scopus 로고    scopus 로고
    • A digital frequency synthesizer for cognitive radio spectrum sensing applications
    • Jun
    • T. Rapinoja et al., "A digital frequency synthesizer for cognitive radio spectrum sensing applications," in Proc. RFIC, Jun. 2009, pp. 423-426.
    • (2009) Proc. RFIC , pp. 423-426
    • Rapinoja, T.1
  • 8
    • 29044450495 scopus 로고    scopus 로고
    • All-digital PLL and transmitter for mobile phones
    • Dec.
    • R. B. Staszewski et al., "All-digital PLL and transmitter for mobile phones," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2469-2482, Dec. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.12 , pp. 2469-2482
    • Staszewski, R.B.1
  • 12
    • 70350247616 scopus 로고    scopus 로고
    • A 5 GHz direct digital synthesizer MMIC with direct modulation and spur randomization
    • Jun
    • X. Geng, F. F. Dai, J. D. Irwin, and R. C. Jaeger, "A 5 GHz direct digital synthesizer MMIC with direct modulation and spur randomization," in Proc. RFIC, Jun. 2009, pp. 419-422.
    • (2009) Proc. RFIC , pp. 419-422
    • Geng, X.1    Dai, F.F.2    Irwin, J.D.3    Jaeger, R.C.4
  • 13
    • 41549140087 scopus 로고    scopus 로고
    • A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance
    • Apr.
    • B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, "A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 855-863, Apr. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.4 , pp. 855-863
    • Helal, B.M.1    Straayer, M.Z.2    Wei, G.-Y.3    Perrott, M.H.4
  • 14
    • 67651171553 scopus 로고    scopus 로고
    • A low power DLL-based clock generator in open-loop mode
    • Jul.
    • B. Mesgarzadeh and A. Alvandpour, "A low power DLL-based clock generator in open-loop mode," IEEE J. Solid-State Circuits, vol.44, no.7, pp. 855-863, Jul. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.7 , pp. 855-863
    • Mesgarzadeh, B.1    Alvandpour, A.2
  • 15
    • 28144449945 scopus 로고    scopus 로고
    • A 3 Gb/s 8b singleended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients
    • Feb.
    • S.-J. Bae, H.-J. Chi, H.-R. Kim, and H.-J. Park, "A 3 Gb/s 8b singleended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients," in Proc. Inst. Solid-State Circuits Conf. Tech. Dig., Feb. , pp. 520-614.
    • Proc. Inst. Solid-State Circuits Conf. Tech. Dig. , pp. 520-614
    • Bae, S.-J.1    Chi, H.-J.2    Kim, H.-R.3    Park, H.-J.4
  • 16
    • 0028495069 scopus 로고
    • Frequency mixer with a frequency doubler for integrated circuits
    • Sep.
    • K. Kimura and H. Asazawa, "Frequency mixer with a frequency doubler for integrated circuits," IEEE J. Solid-State Circuits, vol.29, no.9, pp. 1133-1137, Sep. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , Issue.9 , pp. 1133-1137
    • Kimura, K.1    Asazawa, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.