Architecture of high-performance frequency and phase synthesis

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 6, 2000, Pages 835-846

  Mair, Hugh ^a   Xiu, Liming ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; FREQUENCY DOMAIN ANALYSIS; PHASE LOCKED LOOPS; SPREAD SPECTRUM COMMUNICATION; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK GENERATION; JITTER ANALYSIS;

FREQUENCY SYNTHESIZERS;

EID: 0033703262     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.845187     Document Type: Article

References (14)

1. D. P. Noel and T. A. Kwasniewski, "Frequency synthesis: A comparison of techniques," in Proc. 1994 Canadian Conf. Electrical and Computer Engineering, vol. 2, p. 834.
2. B. G. Goldberg, "Digital frequency synthesis, 1. Reviewing various techniques for synthesizing signals," Microwave & RF, vol. 35, no. 5, pp. 181-185, May 1996.
3. R. E. Best, Phase-Locked Loops: Theory, Design and Application, 3rd ed. New York, NY: McGraw-Hill, 1997.
4. F. M. Gardner, Phase Lock Techniques, 2nd ed. New York, NY: Wiley, 1979.
5. H. Eisenson, "Frequency synthesis using DDS/NCO technology, a tutorial," in Electro Int. Conf. Record, Electron Conventions Manage., Ventura, CA, 1991, pp. 400-418.
6. D. P. Owen and J. N. Wells, "Fractional-N synthesis system," GEC-Review, vol. 11, no. 1, pp. 3-10, 1996.
7. T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-Sigma modulation in fractional-n frequency synthesis," IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
8. M. P. Abadia and A. F. Duran, "A contribution to DECT in frequency synthesis and modulation using DDS," in Proc. 43rd IEEE Vehicular Technology Conf., Secaucus, NJ, May 1993, pp. 949-952.
9. F. M. Gardner, "Charge-pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, Nov. 1980.
10. H. C. Gundrum and M. E. Rizkalla, "Maximizing the stability region for a second order PLL system," in Proc. 37th Midwest Symp. Circuit and System, vol. 2, 1994, pp. 1343-1346.
11. F. Salvatti, "Technique eases design of phase-locked loops," EDN, vol. 35, no. 17, pp. 141-146, Aug. 1990.
12. J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillator," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
13. B. Kim, D. N. Helman, and P. R. Gray, "A 30-MHz hybrid analog/digital clock recovery circuit in 2-μm CMOS," IEEE J. Solid-State Circuits, vol. 25, pp. 1385-1394, Dec. 1990.
14. P. Larsson, "A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction," in ISSCC' 99, Session 20/Paper WA 20.6, pp. 356-357.