Multimode clock generation using delay-locked loop

Electronics Letters

Volumn 39, Issue 4, 2003, Pages 347-349

  Susplugas, O ^a   Philippe, P ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL TO ANALOG CONVERSION; FREQUENCY DOMAIN ANALYSIS; FREQUENCY SYNTHESIZERS; PHASE LOCKED LOOPS; PHASE MODULATION; PHASE SHIFT;

MULTIMODE CLOCK GENERATION;

ELECTRIC DELAY LINES;

EID: 0037456484     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030268     Document Type: Article

References (3)

1. RILEY, T.I.D., COPELAND, M.A., and KWASNIESKI, T.A.: 'Delta-sigma modulation in fractional-N frequency synthesis', IEEE J Solid-State Circuits, 1993, 28, (5)
2. CHIEN, G., and GRAY, P.: 'A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications'. ISSCC, San Francisco, CA, USA, 2000
3. NORSWORTHY, S.R., SCHREIER, R., and TEMES, G.C.: 'Delta-sigma-converters' (IEEE Press)