A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Bae, Seung Jun ^a   Chi, Hyung Joon ^a   Kim, Hyung Rae ^a   Park, Hong June ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144449945     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. E. Yeung, M. Horowitz, "A 2.4Gb/s/pin Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation," IEEE J. Solid-State Circuits, vol. 35, pp. 1619-1628, Nov., 2000.
2. J.Y. Sim et. al, "A CMOS Transceiver for DRAM Bus System with a Demultiplexed Equalization Scheme," IEEE J. Solid-State Circuits, vol. 37, pp. 245-250, Feb., 2002.
3. K.-L. J. Wong et. al, "A 27mW 3.6-Gb/s I/O Transceiver," IEEE J. Solid-State Circuits, vol. 39, pp. 602-612, Apr., 2004.
4. M.Q. Le et. al, "A 3.125Gbps Timing and Data Recovery Front-End with Adaptive Equalization," Symp. VLSI Circuits, pp. 344-347, June, 2004.