Eliminating the fanout bottleneck in parallel long BCH encoders

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 3, 2004, Pages 512-516

  Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; COMMUNICATION CHANNELS (INFORMATION THEORY); ERROR CORRECTION; OPTICAL COMMUNICATION; POLYNOMIALS; WHITE NOISE;

ADDITIVE WHITE GAUSSIAN NOISE; CYCLIC REDUNDANCY CHECKING; LINEAR FEEDBACK SHIFT REGISTERS; PARALLEL PROCESSING; REED-SOLOMON CODES;

ENCODING (SYMBOLS);

EID: 1942453871     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.823655     Document Type: Article

References (7)

1. T.-B. Pei and C. Zukowski, "High-speed parallel CRC circuits in VLSI," IEEE Trans. Commun., vol. 40, pp. 653-657, Apr. 1992.
2. J. H. Derby, "High-speed CRC computation using state-space transformation," in Proc; Global Telecommunications Conf. 2001, GLOBECOM '01, vol. 1, pp. 166-170.
3. R. J. Glaise, "A two-step computation of cyclic redundancy code CRC-32 for ATM networks," IBM J. Res. Dev., vol. 41, pp. 705-709, 1997.
4. K. K. Parhi, VLSI Digital Signal Processing Systems-Design and Implementation. New York: Wiley, 1999.
5. K. K. Parhi, "System and method for generating cyclic codes for error control in digital communications," U.S. Patent Application 678 910, 2002.
6. K. K. Parhi and D. G. Messerschmitt, "Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition," IEEE Trans. Acoustics, Speech, Signal Processing, , vol. 37, pp. 1099-1117, July 1989.
7. C. Leiserson, F. Rose, and J. Sax, "Optimizing synchronous circuitry by retiming," in Proc. 3rd Caltech Conf. VLSI, 1983, pp.