Ultra folded high-speed architectures for reed-solomon decoders

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2006, Issue , 2006, Pages 517-520

  Seth, Kavish ^a   Viswajith, K N ^b   Srinivasan, S ^c   Kamakoti, V ^c  

^a Atheros India LLC   (India)

^b TATA CONSULTANCY SERVICES   (India)

^c INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR-EVALUATOR POLYNOMIALS; MULTIPLIERS; REED-SOLOMON CODES; SYSTOLIC ARRAY ARCHITECTURES;

DECODING; ELECTRIC POWER UTILIZATION; ERROR DETECTION; MULTIPLYING CIRCUITS; POLYNOMIALS; VLSI CIRCUITS;

COMPUTER ARCHITECTURE;

EID: 33748561485     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.163     Document Type: Conference Paper

References (7)

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3. W.Wilheim, "A new scalable VLSI architecture for Reed-Solomon decoders, " IEEE J.Solid-State Circuits, vol.34, pp. 388-396, Mar 1999.
4. E.R.Berlekamp, G.Seroussi, and P.Tong, "Reed-Solomon Codes and Their Applications," S.B.Wicker and V.K.Bhargava, Eds. Piscataway, NJ: IEEE Press, 1994. a hypersystolic Reed-Solomon decoder.
5. HM.Shao, T.K.Truong, L.J.Deutsch, J.H.Yuen and I.S.Reed, "A VLSI design of a pipeline Reed-Solomon decoder," IEEE Trans. Comput., vol. C-34, pp.393-403, May1985.
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7. Dilip V. Sarwate and Naresh R. Shanbhag, "High-Speed Architectures for Reed-Solomon Decoders," IEEE Trans. On Very Large Scale Integration, vol 9, No. 5, October 2001.