High-speed architectures for parallel long BCH encoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 7, 2005, Pages 872-877

  Zhang, Xinmiao ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

Bose Chaudhuri Hocquenghen (BCH); Critical loop; Encoder; Fanout; Generator polynomial; Iteration bound; Linear feedback shift register (LFSR); Parallel processing; Retiming; Unfolding

Indexed keywords

BROADCASTING; COMPUTER ARCHITECTURE; ENCODING (SYMBOLS); FEEDBACK; ITERATIVE METHODS; OPTICAL COMMUNICATION; POLYNOMIALS;

BOSE-CHAUDHURI-HOCQUENGHEN (BCH); CRITICAL LOOP; ENCODER; FANOUT; GENERATOR POLYNOMIAL; ITERATION BOUND; LINEAR FEEDBACK SHIFT REGISTER (LFSR); PARALLEL PROCESSING; RETIMING; UNFOLDING;

PARALLEL PROCESSING SYSTEMS;

EID: 27644565121     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.850125     Document Type: Article

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