메뉴 건너뛰기




Volumn , Issue , 2005, Pages 179-182

Optimized design for high-speed parallel BCH encoder

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTICAL COMMUNICATION; OPTIMIZATION; POLYNOMIALS; SHIFT REGISTERS;

EID: 23844437334     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (8)
  • 2
    • 0035336730 scopus 로고    scopus 로고
    • Automatic generation of parallel CRC circuits
    • M. Sprachmann, "Automatic generation of parallel CRC circuits, " Journal , IEEE Design and Test of Computers, 3(18),pp. 108-114,2001.
    • (2001) Journal, IEEE Design and Test of Computers , vol.3 , Issue.18 , pp. 108-114
    • Sprachmann, M.1
  • 5
    • 1942453871 scopus 로고    scopus 로고
    • Eliminating the fanout bottleneck in parallel long BCH encoders
    • K.K.Parhi, "Eliminating the fanout bottleneck in parallel long BCH encoders, " Journal, IEEE Trans on Circuits and Systems, 3(51),pp.512-516, 2004.
    • (2004) Journal, IEEE Trans on Circuits and Systems , vol.3 , Issue.51 , pp. 512-516
    • Parhi, K.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.