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Volumn , Issue , 2005, Pages 179-182
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Optimized design for high-speed parallel BCH encoder
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COMBINATORIAL CIRCUITS;
ERROR CORRECTION;
INTEGRATED CIRCUIT LAYOUT;
LOGIC GATES;
OPTICAL COMMUNICATION;
OPTIMIZATION;
POLYNOMIALS;
SHIFT REGISTERS;
BCH ENCODER;
CMOS TECHNOLOGY;
ENCODER DESIGN;
LINEAR FEEDBACK SHIFT REGISTER (LFSR);
ENCODING (SYMBOLS);
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EID: 23844437334
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (10)
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References (8)
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