Dependence of DC parameters on layout and low-frequency noise behavior in strained-si nMOSFETs fabricated by stress-memorization technique

IEEE Electron Device Letters

Volumn 31, Issue 5, 2010, Pages 500-502

  Huang, Yao Tsung ^a   Wu, San Lein ^b   Chang, Shoou Jinn ^a   Kuo, Cheng Wen ^a   Chen, Ya Ting ^a   Cheng, Yao Chin ^c   Cheng, Osbert ^c  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b CHENG SHIU UNIVERSITY   (Taiwan)

^c UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Layout geometry; Low frequency; Stress memorization technique (SMT); Unified model

Indexed keywords

CONTROL DEVICE; DC PARAMETERS; INTERFACE QUALITY; LOW FREQUENCY; LOW-FREQUENCY NOISE; NMOSFET; NMOSFETS; ON STATE CURRENT; SMT PROCESS; STRAINED-SI; UNIFIED MODEL;

COMPUTATIONAL GEOMETRY; CONTROL; ELECTRIC BREAKDOWN; MOSFET DEVICES;

TENSILE STRAIN;

EID: 77951877745     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2044477     Document Type: Article

References (15)

1. C.W.Liu, S.Maikap, and C.Y.Yu, "Mobility-enhancement technologies," IEEE Circuits Devices Mag., vol.21, no.3, pp. 21-36, May/Jun. 2005.
2. Y. Luo and D. K. Nayak, "Enhancement of CMOS performance by process-induced stress," IEEE Trans. Semicond. Manuf., vol.18, no.1, pp. 63-68, Feb. 2005. (Pubitemid 40245400)
3. M. H. Liao, L. Yeh, T.-L. Lee, C. W. Liu, and M.-S. Liang, "Superior n-MOSFET performance by optimal stress design," IEEE Electron Device Lett., vol.29, no.4, pp. 402-404, Apr. 2008. (Pubitemid 351486794)
4. G. Eneman, M. Jurczak, P. Verheyen, T. Hoffmann, A. De Keersgieter, and K. De Meyer, "Scalability of strained nitride capping layers for future CMOS generations," in Proc. ESSDERC, 2005, pp. 449-452. (Pubitemid 44816123)
5. C.-H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M.-S. Liang, "Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application," in VLSI Symp. Tech. Dig., 2004, pp. 56-57.
6. A. Wei, M. Wiatr, A. Gehring, R. Boschke, C. Scott, J. Hoentschel, S. Duenkel, M. Gerhardt, T. Feudel, M. Lenski, F. Wirbeleit, R. Otterbach, R. Callahan, G. Koerner, N. Krumm, D. Greenlaw, M. Raab, and M. Horstmann, "Multiple stress memorization in advanced SOI CMOS technologies," in VLSI Symp. Tech. Dig., 2007, pp. 216-217.
7. G. Ghibaudo and T. Boutchacha, "Electrical noise and RTS fluctuations in advanced CMOS devices," Microelectron. Reliab., vol. 42, no. 4/5, pp. 573-582, Apr./May 2002. (Pubitemid 34498204)
8. G. Ghibaudo, O. Roux, C. Nguen-Duc, F. Balestra, and J. Brini, "Improved analysis of low frequency noise in field-effect MOS transistors," Phys. Stat. Sol.(A), vol.124, no.2, pp. 571-581, Apr. 1991.
9. M. P. Lu, W. C. Lee, and M. J. Chen, "Improved 1/f noise characteristics in locally strained Si CMOS using hydrogen-controlled stress liners and embedded SiGe," in VLSI Symp. Tech. Dig., 2006, pp. 104-105.
10. Y. P. Wang, S. L. Wu, and S. J. Chang, "Low-frequency noise characteristics in strained-Si nMOSFETs," IEEE Electron Device Lett., vol.28, no.1, pp. 36-38, Jan. 2007. (Pubitemid 46043863)
11. H. Y. Lin, S. L. Wu, S. J. Chang, Y. P. Wang, and C. W. Kuo, "Low-frequency noise of strained-Si nMOSFETs fabricated on a chemical-mechanical-polished SiGe virtual substrate," Semicond. Sci. Technol., vol.23, no.10, pp. 1-4, Oct. 2008.
12. J. S. Lim and S. E. Thompson, "Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs," IEEE Electron Device Lett., vol.25, no.11, pp. 731-733, Nov. 2004.
13. L. K. J. Vandamme and F. N. Hooge, "What do we certainly know about 1/f noise in MOSTs?," IEEE Trans. Electron Devices, vol.55, no.11, pp. 3070-3085, Nov. 2008.
14. O. Marinov and M. J. Deen, "Low-frequency noise partition of asymmetric MOS transistors operating in linear regime," IEEE Electron Device Lett., vol.30, no.8, pp. 840-842, Aug. 2009.
15. J. Zhuge, R. Wang, R. Huang, Y. Tian, L. Zhang, D.-W. Kim, D. Park, and Y. Wang, "Investigation of low-frequency noise in silicon nanowire MOSFETs," IEEE Electron Device Lett., vol.30, no.1, pp. 57-60, Jan. 2009.