Cost-effective graceful degradation in speculative processor subsystems: The branch prediction case

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 194-197

  Almukhaizim, Sobeeh ^a   Verdel, Thomas ^a   Makris, Yiorgos ^a  

^a Yale University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CODES (SYMBOLS); COMPUTER SIMULATION; ERROR CORRECTION; ERRORS; FINITE AUTOMATA; MICROPROCESSOR CHIPS; PERFORMANCE; REDUNDANCY;

BRANCH PREDICTORS; FINITE STATE MACHINE; HAMMING CODES; PATTERN HISTORY TABLE; SOFTWARE PACKAGE SIMPLESCALAR; SPECULATIVE PROCESSOR SUBSYSTEMS; TRIPLE MODULAR REDUNDANCY;

INTEGRATED CIRCUIT TESTING;

EID: 0345413275     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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