Low-cost, software-based self-test methodologies for performance faults in processor control subsystems

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 263-266

  Almukhaizim, Sobeeh ^a   Petrov, Peter ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; COMPUTER AIDED ANALYSIS; COMPUTER CONTROL SYSTEMS; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS;

HARD-TO-TEST PERFORMANCE FAULTS; PROCESSOR CONTROL SUBSYSTEMS; SOFTWARE BASED SELF TEST;

INTEGRATED CIRCUIT TESTING;

EID: 0034834938     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2001.929769     Document Type: Article

References (9)

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5. Performance test case generation for microprocessors
6. The agree predictor: A mechanism for reducing negative branch history interference
7. A comparison of dynamic branch predictors that use two levels of branch history