Design of a 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipelined ADC

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 4, 2010, Pages 719-730

  Rajaee, Omid ^a   Musah, Tawfiq ^a   Maghari, Nima ^a   Takeuchi, Seiji ^b   Aniya, Mitsuru ^b   Hamashita, Koichi ^b   Moon, Un Ku ^a  

^a 1148 Kelley Engineering Center Corvallis   (United States)

^b Asahi Kasei Microsystems   (Japan)

Author keywords

Delta sigma modulation; Feedback DAC; Loop filter; Noise shaping; Oversampling converters; Pipelined analog to digital converters; Switched capacitor circuits

Indexed keywords

CMOS PROCESSS; DELTA SIGMA MODULATOR; DYNAMIC RANGE; HIGH RESOLUTION; HIGHER RESOLUTION; LOOP FILTER; NOISE-SHAPING; OVER SAMPLING; OVER SAMPLING RATIO; PIPELINED ANALOG-TO-DIGITAL CONVERTER; POWER DISSIPATION; PROTOTYPE CHIP; SWITCHED CAPACITOR CIRCUITS;

ANALOG CIRCUITS; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; DIGITAL INTEGRATED CIRCUITS; MULTICARRIER MODULATION;

MODULATORS;

EID: 77950217253     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2042246     Document Type: Article

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