Analytical analysis of nanoscale fully depleted Double-Gate MOSFETs including the hot-carrier degradation effects

International Journal of Electronics

Volumn 97, Issue 2, 2010, Pages 119-127

  Ghoggali, Z ^a   Djeffal, F ^a  

^a UNIVERSITY OF BATNA   (Algeria)

Author keywords

DG MOSFET; DIBL; Hot carrier; Nanoscale; Surface potential; Threshold voltage

Indexed keywords

2-D NUMERICAL SIMULATION; ANALYTICAL ANALYSIS; ANALYTICAL MODEL; CHANNEL LENGTH; DEVICE DEGRADATION; DEVICE PARAMETERS; DG MOSFETS; DIBL EFFECTS; DOUBLE-GATE MOSFETS; DRAIN-INDUCED BARRIER LOWERING; FULLY DEPLETED; HOT CARRIER DEGRADATION; HOT CARRIER EFFECT; INTERFACE CHARGE; NANO SCALE; NANO-SCALE SURFACES; NEW DEVICES; SHORT CHANNELS;

DEGRADATION; GALERKIN METHODS; MOSFET DEVICES; SURFACE POTENTIAL; SURFACE PROPERTIES; THRESHOLD VOLTAGE; TWO DIMENSIONAL;

NANOSTRUCTURED MATERIALS;

EID: 77949493340     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/00207210902894746     Document Type: Article

References (14)

1. Diagne, B., Prégaldiny, F., Lallment, C., Sallese, J.-M., and Krummenacher, F. (2008), 'Explicit Compact Model for Symmetric Double-gate MOSFETs Including Solutions for Small-geometry Effects', Solid-State Electron, 52, 99-106.
2. Djeffal, F., Chahdi, M., Benhaya, A., and Hafiane, M.L. (2007a), 'An Approach Based on Neural Computation to Simulate the Nanoscale CMOS Circuits: Application to the Simulation of CMOS Inverter', Solid-State Electron, 51, 48-56.
3. Djeffal, F., Dibi, Z., Hafiane, M.L., and Arar, D. (2007b), 'Design and Simulation of a Nanoelectronics DG MOSFET Current Source Using Artificial Neural Networks', Materials Science and Engineering C, 27, 1111-1116.
4. Djeffal, F., Guessasma, S., Benhaya, A., and Chahdi, M. (2005), 'An Analytical Approach Based on Neural Computation to Estimate the Life Time of Deep Submicron MOSFETs', Semiconductor Science and Technology, 20, 158-164.
5. Fossum, J.G., Ge, L., and Chiang, M.H. (2002), 'Speed Superiority of Scaled Double-gate CMOS', IEEE Transactions on Electron Devices, 49, 808-811.
6. Ho, C.S., Huang, K.-Y., Tang, M., and Liou, J.J. (2005), 'An Analytical Threshold Voltage Model of NMOSFETs with Hot-carrier Induced Interface Charge Effect', Microelectrinics Reliability, 45, 1144-1149.
7. ITRS (2005), International Technology Roadmap for Semiconductors, http://www.itrs.org
8. Jean, Y.S., and Wu, C.Y. (1997), 'The Threshold Voltage Model of MOSFET Devices with Localized Interface Charge', IEEE Transactions on Electron Devices, 44, 441-447.
9. Lee, G.H., Su, J.S., and Chung, S. (1996), 'A New Method for Characterizing the Spatial Distributions of Interface States and Oxide-trapped Charges in LDD n-MOSFETs', IEEE Transactions on Electron Devices, 43, 81-89.
10. Park, J.T., Choi, N.J., Yu, C.G., Jeon, S.H., and Colinge, J.-P. (2003), 'Increased Hot Carrier Effects in Gate-All-Around SOI nMOSFET's', Microelectronics Reliability, 43, 1427-1432.
11. Singh, A.K. (2008), 'An Analytical Study of Hot Carrier Degradation Effects in Sub-micron MOS Devices', European Journal of Applied Physics, 42, 87-94.
12. Taur, Y. (2000), 'An Analytical Solution to a Double-gate MOSFET with Undoped Body', IEEE Electron Device Letter, 21, 245-247.
13. Young, K.K. (1989), 'Analysis of Conduction in Fully-Depleted SOI MOSFETs', IEEE Transactions on Electron Devices, 36, 504-506.
14. Zhibin, R., Venugopal, R., Goasguen, S., Datta, S., and Lundstrom, M.S. (2003), 'NanoMOS 2.5: a Two-dimensional simulator for Quantum Transport in Double-gate MOSFETs', IEEE Transactions on Electron Devices, 50, 1914-1925.