Soft error filtered and hardened latch

ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Volumn , Issue , 2009, Pages 613-616

  Alidash, Hossein Karimiyan ^a   Sayedi, Sayed Masoud ^a   Saidi, Hossein ^a   Oklobdzija, Vojin G ^b  

^a ISFAHAN UNIVERSITY OF TECHNOLOGY   (Iran)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

Latch; Reliability; Skewed CMOS; Soft error

Indexed keywords

90NM CMOS; COMBINATIONAL LOGIC; FEED-BACK LOOP; INPUT SET; INTERNAL NODES; LATCH; LATCH CIRCUITS; LOW POWER; LOW-POWER CONSUMPTION; POST LAYOUT SIMULATION; SET-UP TIME; SINGLE PARTICLE; SOFT ERROR;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; HARDENING; TRANSIENTS;

TIMING CIRCUITS;

EID: 77949450997     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASICON.2009.5351360     Document Type: Conference Paper

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