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Volumn , Issue , 2009, Pages 135-142

FPGA implementation of an invasive computing architecture

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING ARCHITECTURE; DYNAMIC RE-CONFIGURATION; DYNAMICALLY RECONFIGURABLE ARCHITECTURE; FPGA IMPLEMENTATIONS; HARDWARE COST; PROCESSOR ARCHITECTURES; RECONFIGURABLE PLAT-FORMS; RESOURCE AWARE; RUNTIMES;

EID: 77949394195     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2009.5377633     Document Type: Conference Paper
Times cited : (6)

References (16)
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    • K. Asanovic, R. Bodik, B. Catanzaro, J. Gebis, P. Husbands, K. Keutzer, D. Patterson, W. Plishker, J. Shalf, S. Williams et al., "The Landscape of Parallel Computing Research: A View from Berkeley," Electrical Engineering and Computer Sciences, University of California at Berkeley, Technical Report No. UCB/EECS-2006-183, December, vol. 18, no. 2006-183, p. 19, 2006.
  • 3
    • 38549135754 scopus 로고    scopus 로고
    • Mapping a Class of Dependence Algorithms to Coarse-Grained Reconfigurable Arrays: Architectural Parameters and Methodology
    • F. Hannig, H. Dutta, and J. Teich, "Mapping a Class of Dependence Algorithms to Coarse-Grained Reconfigurable Arrays: Architectural Parameters and Methodology," International Journal of Embedded Systems, vol. 2, no. 1, pp. 114-127, 2006.
    • (2006) International Journal of Embedded Systems , vol.2 , Issue.1 , pp. 114-127
    • Hannig, F.1    Dutta, H.2    Teich, J.3
  • 5
    • 77949370311 scopus 로고    scopus 로고
    • Invasive Algorithms and Architectures, it
    • J. Teich, "Invasive Algorithms and Architectures," it - Information Technology, vol. 50, no. 5, pp. 300-310, 2008.
    • (2008) Information Technology , vol.50 , Issue.5 , pp. 300-310
    • Teich, J.1
  • 8
    • 58849136300 scopus 로고    scopus 로고
    • Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations
    • S. Banerjee, E. Bozorgzadeh, and N. Dutt, "Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 2, pp. 234-247, 2009.
    • (2009) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.17 , Issue.2 , pp. 234-247
    • Banerjee, S.1    Bozorgzadeh, E.2    Dutt, N.3
  • 9
    • 33646940730 scopus 로고    scopus 로고
    • A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [Multimedia Applications]
    • J. Resano, D. Mozos, and F. Catthoor, "A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [Multimedia Applications]," in Design, Automation and Test in Europe, 2005. Proceedings, 2005, pp. 106-111.
    • (2005) Design, Automation and Test in Europe, 2005. Proceedings , pp. 106-111
    • Resano, J.1    Mozos, D.2    Catthoor, F.3
  • 11
    • 33644643030 scopus 로고    scopus 로고
    • Marching-Pixels: A new Organic Computing Paradigm for Smart Sensor Processor Arrays
    • ACM New York, NY, USA
    • D. Fey and D. Schmidt, "Marching-Pixels: A new Organic Computing Paradigm for Smart Sensor Processor Arrays," in Proceedings of the 2nd conference on Computing frontiers. ACM New York, NY, USA, 2005, pp. 1-9.
    • (2005) Proceedings of the 2nd conference on Computing frontiers , pp. 1-9
    • Fey, D.1    Schmidt, D.2
  • 14
    • 40349113716 scopus 로고    scopus 로고
    • CAPSULE: Hardware-assisted Parallel Execution of Component-Based Programs
    • Washington, DC, USA, pp
    • P. Palatin and O. Temam, "CAPSULE: Hardware-assisted Parallel Execution of Component-Based Programs," IEEE Computer Society Washington, DC, USA, pp. 247-258, 2006.
    • (2006) IEEE Computer Society , pp. 247-258
    • Palatin, P.1    Temam, O.2
  • 16
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    • J. Angermeier, D. Gohringer, M. Majer, J. Teich, S. Fekete, and J. Veen, The Erlangen Slot Machine-A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESMEine Hardware-Plattform fur interdisziplinare Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens), it-Information Technology (vormals it+ ti), 49, no. 3, pp. 143-148, 2007.
    • J. Angermeier, D. Gohringer, M. Majer, J. Teich, S. Fekete, and J. Veen, "The Erlangen Slot Machine-A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESMEine Hardware-Plattform fur interdisziplinare Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)," it-Information Technology (vormals it+ ti), vol. 49, no. 3, pp. 143-148, 2007.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.