Integrated microfluidic cooling and interconnects for 2D and 3D chips

IEEE Transactions on Advanced Packaging

Volumn 33, Issue 1, 2010, Pages 79-87

  Dang, Bing ^a   Bakir, Muhannad S ^b   Sekar, Deepak Chandra ^c   King Jr , Calvin R ^b   Meindl, James D ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Microelectronics Research Center   (United States)

^c SanDisk Corporation   (United States)

Author keywords

3D integration; Assembly; Fluidic input output (I O) interconnect; Microchannel heat sink; Microfluidic cooling; Packaging; Stacking; Thermal management

Indexed keywords

3D INTEGRATION; INPUT/OUTPUT; MICRO CHANNEL HEAT SINKS; STACKING; THERMAL MANAGEMENT;

APPROXIMATION THEORY; CHIP SCALE PACKAGES; COOLING; FABRICATION; HEAT RESISTANCE; MICROCHANNELS; MICROFLUIDICS; MONOLITHIC INTEGRATED CIRCUITS; SILICON WAFERS; TEMPERATURE CONTROL; THREE DIMENSIONAL;

HEAT SINKS;

EID: 77749336526     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2009.2035999     Document Type: Article

References (27)

1. International Technology Roadmap for Semiconductors (ITRS), 2006 Update.
2. Various microprocessor datasheets [Online]. Available: http://www.intel.com
3. S. P. Gurrum, S. K. Suman, Y. K. Joshi, and A. G. Fedorov, "Thermal issues in next-generation integrated circuits," IEEE Trans. Device Mater. Rel., vol. 4, no. 4, pp. 709-714, Dec. 2004.
4. Z. J. Zhou, L. R. Hoover, and A. L. Philips, "An integrated thermal architecture for thermal management of high power electronics," in Proc. Int. Conf. THERMES, 2002, pp. 317-336.
5. Tuckerman and R. F. W. Pease, "High performance heat sinking for VLSI," IEEE Electron Device Lett., vol. EDL-2, pp. 126-129, 1981.
6. A. Naeemi and J. D. Meindl, "Impact of deep sub-ambient cooling on GSI interconnect performance," in Proc. IEEE Int. Interconnect Technol. Conf., 2005, pp. 156-158.
7. H. Y. Zhang, D. Pinjala, T. N. Wong, and Y. K. Joshi, "Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations," IEEE Trans. Compon. Packag. Technol., vol. 28, no. 1, pp. 127-135, Mar. 2005.
8. L. Jiang, J. Mikkelsen, J. Koo, D. Huber, S. Yao, L. Zhang, P. Zhou, J. G. Maveety, R. Prasher, J. G. Santiago, T. W. Kenny, and K. E. Goodson, "Closed-loop electroosmotic microchannel cooling system for VLSI circuits," IEEE Trans. Compon. Packag. Technol., vol. 25, no. 3, pp. 347-355, Jun. 2002.
9. D. Liu and S. V. Garimella, "Analysis and optimization of the thermal performance of microchannel heat sinks," Int. J. Numerical Methods Heat Fluid Flow, vol. 15, pp. 7-26, 2005.
10. J.-M. Koo, S. Im, L. Jiang, and K. E. Goodson, "Integrated microchannel cooling for three-dimensional electronic circuit architectures," ASME. J. Heat Transfer, vol. 127, no. 1, pp. 49-58, 2005.
11. M. J. de Boer, R. W. Tjerkstra, J. W. Berenschot, H. V. Jansen, G. J. Burger, J. G. E. Gardeniers, M. Elwenspoek, and A. van den Berg, "Micromachining of buried micro channels in silicon," J. Microelec-tromechan. Syst., vol. 9, no. 1, pp. 94-103, 2000.
12. I. Papautsky, J. Brazzle, H. Swerdlow, and A. B. Frazier, "A low-temperature IC-compatible process for fabricating surface-micromachined metallic microchannels," J. Microelectromechan. Syst., vol. 7, no. 2, pp. 267-273, 1998.
13. J. P. Jayachandran, H. A. Reed, H. Zhen, L. F. Rhodes, C. L. Henderson, S. A. B. Allen, and P. A. Kohl, "Air-channel fabrication for microelectromechanical systems via sacrificial photosensitive polycarbonates," J. Microelectromechan. Syst., vol. 12, no. 2, pp. 147-159, 2003.
14. D. Bhusari, H. A. Reed, M. Wedlake, A. M. Padovani, S. Allen, and P. A. Kohl, "Fabrication of air-channel structures for microfluidic, mi-croelectromechanical, and microelectronic applications," J. Microelec-tromechan. Syst., vol. 10, no. 3, pp. 400-408, 2001.
15. B. Dang, P. J. Joseph, M. S. Bakir, T. Spencer, P. Kohl, and J. Meindl, "Wafer-level microfluidic cooling interconnects for GSI," in Proc. IEEE Int. Interconnect Technol. Conf. (IITC), 2005, pp. 180-182.
16. B. Dang, M. Bakir, and J. Meindl, "Integrated thermofluidic I/O interconnects for an on-chip microchannel heat sink," IEEE Electron Device Lett., vol. 27, no. 2, pp. 117-119, 2006.
17. R. Bauer, V. Strickert, K.-J. Wolter, W. Sauer, D. Leonescu, and P. Svasta, "Investigation on an integrated liquid cooling system in LTCC-multilayer," in Proc. 24th Int. Spring Seminar Electron. Technol.: Concurrent Eng. Electron. Packag., 2001, pp. 178-182.
18. H. Ilgen, "Water-cooled multilayer printed circuit board," Elektronik, vol. 48, no. 19, pp. 46-52, 1999.
19. W. Qu, R. Green, and M. Austin, "Development of multi-functional sensors in thick-film and thin-film technology," Meas. Sci. Technol., vol. 11, pp. 1111-1118, 2000, (Printed in the UK).
20. J. Early, "Speed, power and component density in multi-element high-speed logic systems," in ISSCC Dig. Tech. Papers, Feb. 1960, pp. 78-79.
21. Interconnect Technology and Design for Gigascale Integration, J. A. Davis and J. D. Meindl, Eds. Norwell, MA: Kluwer Academic, 2003.
22. Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl, Eds. Norwood, MA: Artech House, Nov. 2009.
23. S. Pozder, J.-Q. Lu, Y. Kwon, S. Zollner, J. Yu, J. J. McMahon, T. S. Cale, K. Yu, and R. J. Gutmann, "Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform," in Proc. IEEE Int. Interconnect Technol. Conf., Jun. 2004, pp. 102-104.
24. C. K. King, D. Sekar, M. S. Bakir, B. Dang, J. Pikarsky, and J. D. Meindl, "3D stacking of chips with electrical and microfluidic I/O interconnects," in Proc. Electron. Compon. Technol. Conf., Jun. 2008, pp. 1-7.
25. M. S. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi, and J. D. Meindl, "3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation," in Proc. IEEE Custom Integrated Circuits Conf., 2008, pp. 663-670.
26. D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. S. Bakir, and J. D. Meindl, "A 3D-IC technology with integrated microchannel cooling," in Proc. Int. Interconnect Technol. Conf., Jun. 2008, pp. 13-15.
27. K. Nose and T. Sakurai, "Optimization of VDD and VTH for low-power and high-speed applications," in Proc. Asia South Pacific Design Automat. Conf., 2000, pp. 469-474.