Statistical analysis of large on-chip power grid networks by variational reduction scheme

Integration, the VLSI Journal

Volumn 43, Issue 2, 2010, Pages 167-175

  Li, Duo ^a   Tan, Sheldon X D ^a  

^a University of California Riverside   (United States)

Author keywords

Model order reduction; Power grid analysis; Statistical; Truncated balanced realization

Indexed keywords

ANALYSIS APPROACH; BENCHMARK CIRCUIT; CRITICAL CHALLENGES; DESIGN STAGE; IN-CHIP; LARGE POWER; MODEL ORDER REDUCTION; MONTE CARLO; NUMERICAL INTEGRATIONS; ON-CHIP POWER DISTRIBUTION; ON-CHIP POWER GRIDS; ORIGINAL SYSTEMS; PARAMETERIZED; POWER GRID ANALYSIS; PROCESS VARIABILITY; PROCESS VARIATION; REDUCED SYSTEMS; STATISTICAL ANALYSIS; STATISTICAL SIMULATION; TRUNCATED BALANCED REALIZATIONS; VLSI DESIGN; VOLTAGE DROP;

CIRCUIT THEORY; DISTRIBUTED PARAMETER NETWORKS; ELECTRIC POWER SYSTEMS; GRID COMPUTING; INTERCONNECTION NETWORKS; MONTE CARLO METHODS; POWER GENERATION; VOLTAGE CONTROL;

VARIATIONAL TECHNIQUES;

EID: 77649338400     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2010.01.004     Document Type: Article

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