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Volumn 2005, Issue , 2005, Pages 365-371

Static timing analysis considering power supply variations

Author keywords

[No Author keywords available]

Indexed keywords

NONLINEAR OPTIMIZATION; STATIC TIMING ANALYSIS; SUBMICRON TECHNOLOGY; SUPPLY VARIATIONS;

EID: 33751429476     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560095     Document Type: Conference Paper
Times cited : (24)

References (17)
  • 3
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    • A multigrid-like technique for power grid analysis
    • October
    • J. Kozhaya, S. R. Nassif, and F. N. Najm, "A multigrid-like technique for power grid analysis," in IEEE Trans. on Computer-Aided Design, vol. 21, no. 10, pp. 1148-1160, October 2002.
    • (2002) IEEE Trans. on Computer-aided Design , vol.21 , Issue.10 , pp. 1148-1160
    • Kozhaya, J.1    Nassif, S.R.2    Najm, F.N.3
  • 6
    • 0036045515 scopus 로고    scopus 로고
    • Coping with buffer delay change due to power and ground noise
    • L. H. Chen, M. Sadowska and F. Brewer, "Coping with buffer delay change due to power and ground noise," Proc. DAC, 2002.
    • (2002) Proc. DAC
    • Chen, L.H.1    Sadowska, M.2    Brewer, F.3
  • 7
    • 0034474847 scopus 로고    scopus 로고
    • Path selection and pattern generation for dynamic timing analysis considering power supply noise effects
    • J.-J. Liou, A. Krstic, Y.-M. Jiang and K.-T. Cheng, "Path selection and pattern generation for dynamic timing analysis considering power supply noise effects", in Proc. ICCAD, 2000.
    • (2000) Proc. ICCAD
    • Liou, J.-J.1    Krstic, A.2    Jiang, Y.-M.3    Cheng, K.-T.4
  • 8
    • 0034846652 scopus 로고    scopus 로고
    • Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
    • G. Bai, S. Bobba and I. N. Hajj, "Static timing analysis including power supply noise effect on propagation delay in VLSI circuits", in Proc. DAC, 2001.
    • (2001) Proc. DAC
    • Bai, G.1    Bobba, S.2    Hajj, I.N.3
  • 9
    • 4444315750 scopus 로고    scopus 로고
    • Worst-case circuit delay taking into account power supply variations
    • D. Kouroussis, R. Ahmadi and F. N. Najm, "Worst-case circuit delay taking into account power supply variations", in Proc. DAC, 2004.
    • Proc. DAC, 2004
    • Kouroussis, D.1    Ahmadi, R.2    Najm, F.N.3
  • 11
    • 85087536555 scopus 로고    scopus 로고
    • Timing analysis in presence of power supply and ground voltage variations
    • R. Ahmadi and F. N. Najm, "Timing analysis in presence of power supply and ground voltage variations," in Proc. ICCAD'03
    • Proc. ICCAD'03
    • Ahmadi, R.1    Najm, F.N.2
  • 13
    • 0032685389 scopus 로고    scopus 로고
    • Fast and exact simtitaneom gate and wire sizing by lagrangian relaxation
    • July
    • Chung-Ping Chen, C. C. N. Chu, and D. F. Wong, "Fast and Exact Simtitaneom Gate and Wire Sizing by Lagrangian Relaxation", in IEEE Trans on CAD, vol. 18, no. 7, July 1999.
    • (1999) IEEE Trans on CAD , vol.18 , Issue.7
    • Chen, C.-P.1    Chu, C.C.N.2    Wong, D.F.3
  • 14
    • 33751392788 scopus 로고    scopus 로고
    • A static pattern-independent approach for power grid voltage integrity verification
    • D. Kouroussis and F. N. Najm, "A static pattern-independent approach for power grid voltage integrity verification," in Proc. DAC, 2003.
    • (2003) Proc. DAC
    • Kouroussis, D.1    Najm, F.N.2
  • 15
  • 16
    • 84860023915 scopus 로고    scopus 로고
    • Stanford Business Software Inc. www.sbsi-sol-optimize.com.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.