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Volumn , Issue , 2004, Pages 171-176

A stochastic approach to power grid analysis

Author keywords

IR drop; Ldi dt; Power supply networks

Indexed keywords

CALCULATIONS; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); PROBABILITY DISTRIBUTIONS; RANDOM PROCESSES; STATISTICAL METHODS; WAVEFORM ANALYSIS;

EID: 4444384281     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996616     Document Type: Conference Paper
Times cited : (37)

References (12)
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  • 2
    • 0032597773 scopus 로고    scopus 로고
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  • 4
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    • Fast power grid simulation
    • S. R. Nassif and J. N. Kozhaya, "Fast power grid simulation," in Proc. DAC, pp. 156-161, 2000.
    • (2000) Proc. DAC , pp. 156-161
    • Nassif, S.R.1    Kozhaya, J.N.2
  • 7
    • 0031642709 scopus 로고    scopus 로고
    • Design and analysis of power distribution networks in PowerPC microprocessors
    • A. Dharchoudhury, R. Panda, D. Blaauw and R. Vaidyanathan, "Design and Analysis of Power Distribution Networks in PowerPC microprocessors," in Proc. DAC, 1998.
    • (1998) Proc. DAC
    • Dharchoudhury, A.1    Panda, R.2    Blaauw, D.3    Vaidyanathan, R.4
  • 8
    • 0030672649 scopus 로고    scopus 로고
    • Vector generation for maximum instantaneous current through supply lines for CMOS circuits
    • A. Krstic and K. Cheng, "Vector generation for maximum instantaneous current through supply lines for CMOS circuits," in Proc. DAC, pp. 383-388, 1997.
    • (1997) Proc. DAC , pp. 383-388
    • Krstic, A.1    Cheng, K.2
  • 9
    • 0033359193 scopus 로고    scopus 로고
    • VIP - An input pattern generator for identifying critical voltage drop for deep submicron designs
    • Y. M. Jiang, T. Young and K. Cheng, "VIP - an input pattern generator for identifying critical voltage drop for deep submicron designs," in Proc. ISLPED, pp. 156-161, 1999.
    • (1999) Proc. ISLPED , pp. 156-161
    • Jiang, Y.M.1    Young, T.2    Cheng, K.3
  • 10
    • 0029358733 scopus 로고
    • Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits
    • H. Kriplani, F. Najm, I. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits," in IEEE Trans. on CAD, vol. 14. no. 8, pp. 998-1012, 1995.
    • (1995) IEEE Trans. on CAD , vol.14 , Issue.8 , pp. 998-1012
    • Kriplani, H.1    Najm, F.2    Hajj, I.3
  • 11
    • 84949936414 scopus 로고    scopus 로고
    • RC power bus maximum voltage drop in digital VLSI circuits
    • G. Bai, S. Bobba and I.N. Hajj, "RC power bus maximum voltage drop in digital VLSI circuits," in Proc. ISQED, pp. 205-210, 2001.
    • (2001) Proc. ISQED , pp. 205-210
    • Bai, G.1    Bobba, S.2    Hajj, I.N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.