-
1
-
-
0031619177
-
Full-chip verification methods for DSM power distribution systems
-
G. Steele, D. Overhauser, S. Rochel and Z, Hussain, "Full-chip verification methods for DSM power distribution systems," in Proc. DAC, pp. 744-749, 1998.
-
(1998)
Proc. DAC
, pp. 744-749
-
-
Steele, G.1
Overhauser, D.2
Rochel, S.3
Hussain, Z.4
-
2
-
-
0032597773
-
The challenge of designing global systems in UDSM CMOS
-
S. Taylor, "The challenge of designing global systems in UDSM CMOS," in Proc CICC, pp.429-435, 1999
-
(1999)
Proc CICC
, pp. 429-435
-
-
Taylor, S.1
-
4
-
-
0033683771
-
Fast power grid simulation
-
S. R. Nassif and J. N. Kozhaya, "Fast power grid simulation," in Proc. DAC, pp. 156-161, 2000.
-
(2000)
Proc. DAC
, pp. 156-161
-
-
Nassif, S.R.1
Kozhaya, J.N.2
-
5
-
-
0036474411
-
Hierarchical analysis of power distribution networks
-
M. Zhao, R. V. Panda, S. S. Sapatnekar and D. Blaauw, "Hierarchical analysis of power distribution networks," in IEEE Trans. on CAD, pp. 159-168, 2002.
-
(2002)
IEEE Trans. on CAD
, pp. 159-168
-
-
Zhao, M.1
Panda, R.V.2
Sapatnekar, S.S.3
Blaauw, D.4
-
6
-
-
0033670992
-
Model and analysis for combined package and on-chip power grid simulation
-
R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young and R. Ramaraju, "Model and analysis for combined package and on-chip power grid simulation," in Proc. ISLPED, pp. 179-184, 2000.
-
(2000)
Proc. ISLPED
, pp. 179-184
-
-
Panda, R.1
Blaauw, D.2
Chaudhry, R.3
Zolotov, V.4
Young, B.5
Ramaraju, R.6
-
7
-
-
0031642709
-
Design and analysis of power distribution networks in PowerPC microprocessors
-
A. Dharchoudhury, R. Panda, D. Blaauw and R. Vaidyanathan, "Design and Analysis of Power Distribution Networks in PowerPC microprocessors," in Proc. DAC, 1998.
-
(1998)
Proc. DAC
-
-
Dharchoudhury, A.1
Panda, R.2
Blaauw, D.3
Vaidyanathan, R.4
-
8
-
-
0030672649
-
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
-
A. Krstic and K. Cheng, "Vector generation for maximum instantaneous current through supply lines for CMOS circuits," in Proc. DAC, pp. 383-388, 1997.
-
(1997)
Proc. DAC
, pp. 383-388
-
-
Krstic, A.1
Cheng, K.2
-
9
-
-
0033359193
-
VIP - An input pattern generator for identifying critical voltage drop for deep submicron designs
-
Y. M. Jiang, T. Young and K. Cheng, "VIP - an input pattern generator for identifying critical voltage drop for deep submicron designs," in Proc. ISLPED, pp. 156-161, 1999.
-
(1999)
Proc. ISLPED
, pp. 156-161
-
-
Jiang, Y.M.1
Young, T.2
Cheng, K.3
-
10
-
-
0029358733
-
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits
-
H. Kriplani, F. Najm, I. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits," in IEEE Trans. on CAD, vol. 14. no. 8, pp. 998-1012, 1995.
-
(1995)
IEEE Trans. on CAD
, vol.14
, Issue.8
, pp. 998-1012
-
-
Kriplani, H.1
Najm, F.2
Hajj, I.3
-
11
-
-
84949936414
-
RC power bus maximum voltage drop in digital VLSI circuits
-
G. Bai, S. Bobba and I.N. Hajj, "RC power bus maximum voltage drop in digital VLSI circuits," in Proc. ISQED, pp. 205-210, 2001.
-
(2001)
Proc. ISQED
, pp. 205-210
-
-
Bai, G.1
Bobba, S.2
Hajj, I.N.3
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