Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 856-859

  Ferzli, Imad A ^a   Najm, Farid N ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Leakage current; Power grid; Statistical analysis; Voltage drop

Indexed keywords

ALGORITHMS; ELECTRIC POWER SYSTEMS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; STATISTICAL TESTS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

POWER GRIDS;

SYSTEMS ANALYSIS;

EID: 0043136477     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.776047     Document Type: Conference Paper

References (13)

1. K. A. Bowman, S. G. Duvall, and J. D. Meindl. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution. In ISSCC, pages 278-279, 2001.
2. V. De and S. Borkar. Technology and design challenges for low power and high performance. In ISLPED, pages 163-168, 1999.
3. T. Kam, S. Rawat, D. Kirkpatrick, R. Roy, G. S. Spirakis, N. Sherwani, and C. Peterson. EDA challenges facing future microprocessor design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12);1498-1506, Dec. 2000.
4. T. Karnik, S. Borkar, and V. De. Sub-90nm technologies challenges and opportunities for CAD. In ICCAD, pages 203-206, 2002.
5. H. Kriplani, F. N. Najm, and I. Hajj. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution. IEEE Transactions on Computer-Aided Design, 14(8):998-1012, August 1995.
6. I. R. Miller, J. E. Freund, and R. Johnson. Probability and Statistics for Engineers. Prentice-Hall, Inc., 4th edition, 1990.
7. S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan. Full-chip sub-threshold leakage power prediction model for sub-0.18um CMOS. In ISLPED, pages 19-23, 2002.
8. S. R. Nassif. Within-chip variability analysis. In IEDM, pages 283-286,1998.
9. A. Papoulis. Probability, Random Variables, and Stochastic Processes, McGraw-Hill, 2nd edition, 1984.
10. L. T. Pillage, R. A. Rohrer, and C. Visweswariah. Electronic Circuit and System Simulation Methods, McGraw-Hill, 1995.
11. A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester. Modeling and analysis of leakage power considering within-die process variations. In ISLPED, pages 64-67, 2002.
12. B. E. Stine, D. S. Boning, and J. E. Chung. Analysis and decomposition of spatial variation in integrated circuit processes and devices IEEE Transactions on Semiconductor Manufacturing, 10(1):24-41, Feb. 1997.
13. S. K. Thompson. Sampling. John Wiley & Sons, Inc., 2nd edition, 2002.