510 Gb/s 70 mW burst mode AC coupled receiver in 90-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 3, 2010, Pages 524-537

  Hossain, Masum ^a   Chan Carusone, Anthony ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

AC coupling; Burst mode; Dicode channel; Half rate; Injection locking

Indexed keywords

90NM CMOS; AC COUPLED; AC COUPLING; AREA EFFICIENT; BURST MODE; BURST MODE RECEIVERS; CHANNEL RESPONSE; CLOCK RECOVERY; HALF-RATE; HIGH FREQUENCY COMPONENTS; HIGH-PASS; INJECTION LOCK; INJECTION-LOCKING; LOW FREQUENCY; LOW POWER; LOW-FREQUENCY SIGNALS; NRZ SIGNALS; SIMULATION TECHNIQUE;

ELECTRIC CLOCKS;

SIGNAL RECEIVERS;

EID: 77649107276     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2039535     Document Type: Article

References (24)

1. L. Luo, J. M. Wilson, S. E. Mick, J. Xu, L. Zhang, and P. D. Franzon, "A 3 Gb/s AC coupled chip-to-chip communication using a low swing pulse receiver," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 522-523.
2. K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 mW/pin wireless superconnect (WSC) interface scheme," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 186-127.
3. A. Fazzi et al., "3D capacitive interconnections with mono- and bidirectional capabilities," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 356-357.
4. E. Fang, G. Asada, R. Kumar, S. Hale, P. Ken, and M. Leary, "A 5.2 Gb/s hypertransport integrated ac coupled receiver with DFR DC restore," in IEEE Symp. VLSI Circuits Dig., Jun. 2007, pp. 34-35.
5. R. Drost, R. Hopkins, R. Ho, and I. Sutherland, "Proximity communication," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1529-1535, Sep. 2004.
6. A. Tajalli, P. Muller, and Y. Leblebici, "A power-efficient clock and data recovery circuit in 0.18-μm CMOS technology for multi-channel short-haul optical data communication," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2288-290, Oct. 2007.
7. N. Miura et al., "An 11 Gb/s inductive-coupling link with burst transmission," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 288-290.
8. M. Nogawa et al., "A 10 Gb/s burst-mode CDRIC in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 228-229.
9. M. Hossain and A. Chan Carusone, "A 14 gb/s 32 mW AC coupled receiver in 90-nm cmos," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2007, pp. 186-187.
10. J. Lee and M. Liu, "A 20-Gb/s burst-mode clock and data recovery circuit using injection-locking technique," IEEE J. Solid-State Circuits, vol. 55, no. 3, pp. 619-630, Mar. 2008.
11. C.-F. Liang, S.-C. Hwu, and S.-I. Liu, "A 10 Gbps burst-mode CDR circuit in 0.18 μm CMOS," in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2006.
12. Murata and T. Otsuji, "A novel clock recovery circuit for fully monolithic integration," IEEE Microw. Theory Tech., vol. 12, no. 12, pp. 2528-2533, Dec. 1999.
13. R. W. Wood and R. W. Donaldson, "Decision feedback equalization of the DC null in high-density digital magnetic recording," IEEE Trans. Magn., vol. 14, pp. 218-221, Jul. 1978.
14. S. Galal and B. Razavi, "10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2138-2146, Dec. 2003.
15. P. Monteiro, J. Matos, A. Gamerio, and J. Rocha, "10 Gb/s timing recovery circuit using dielectric resonators and active bandpass filters," IEEE Electron. Lett., vol. 28, Apr. 1992.
16. B. Casper and F. O'Mahony, "Clocking analysis, implementation and measurement techniques for high-speed data links a tutorial," IEEE Trans. Circuits Syst. I, vol. 56, no. 1, pp. 683-688, Jan. 2009.
17. J. Zhan, J. Duster, and K. Kornegay, "Full-rate injection-locked 10.3 Gb/s clock and data recovery circuit in a 45 GHz ft SiGe process," in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2005, vol. 2.
18. R. Adler, "A study of locking phenomena in oscillators," Proc. IRE, vol. 33, pp. 351-357, Jun. 1946.
19. L. J. Paciorek, "Injection locking of oscillators," Proc. IEEE, vol. 53, pp. 1723-1728, Nov. 1965.
20. M. Hossain and A. Chan Carusone, "CMOS oscillators for clock distribution and injection-locked deskew," IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2138-2153, Aug. 2009.
21. H. R. Rategh and T. H. Lee, "Superharmonic injection-locked frequency dividers," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813-821, Jun. 1999.
22. B. Razavi, Design of Integrated Circuits for Optical Communications, 1st ed. Cambridge, U.K.: Cambridge Univ. Press, 2002.
23. B. Razavi, "A study of phase noise in CMOS oscillators," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331-343, Mar. 1996.
24. F. O'Mahony et al., "A 27 Gb/s forwarded clock I/O receiver using an injection-locked LC-DCO in 45 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.