A 5.2Gbps HyperTransport™ integrated AC coupled receiver with DFR DC restore

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 34-35

  Fang, Emerson ^a   Asada, Gladney ^a   Kumar, Rohit ^a   Hale, Stephen ^a   Leary, Mike ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

AC coupling; DC restore and decision feedback restore; HyperTransport ; Receiver

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA REDUCTION; DC MOTORS; DECISION FEEDBACK EQUALIZERS; SEMICONDUCTING SILICON;

AC COUPLING; DATA RATE; DECISION FEEDBACK RESTORE (DPR) METHOD; HYPERTRANSPORT REVISION 3 (HT3);

SIGNAL RECEIVERS;

EID: 39749085809     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342755     Document Type: Conference Paper

References (4)

1. HyperTransport™ I/O Link Specification Revision 3.0, http://www.hypertransport.org/tech/tech_specs.cfm
2. M. Kandlikar and I. Jacobs, "'Analysis of Quantized Feedback Low-Frequency Restoration in Digital Regenerators,''' IEEE Trans. Communications, Vol. 38, No 8. pp. 1118-1120, August 1990.
3. M. Shakiba, "A 2,5Gb/s Adaptive Cable Equalizer." ISSCC Digest, pp. 396-397, 1999.
4. J. Dorsey, S. Searles. M. Ciraula. E. Fang, S. Johnson, N. Bujanos, R. Kumar, D. Wu, M. Braganza, S. Meyers. "An Integrated Quad-Core Opteron™ Processor," ISSCC Digest, 2007, to be published.