A 10Gbps burst-mode CDR circuit in 0.18μm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 599-602

  Liang, Che Fu ^a   Hwu, Sy Chyuan ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CLOCKS; INTERPOLATION; JITTER; NETWORKS (CIRCUITS);

DIGITAL PHASE INTERPOLATOR; PHASE-ALIGNING LOOP; QUADRATURE GENERATOR;

DATA REDUCTION;

EID: 39049157323     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320828     Document Type: Conference Paper

References (6)

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2. M. Banu, and A. E. Dunlop, "A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission," IEEE International Solid-State Circuits Conference, pp. 102-103, Feb. 1995.
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