Trade-offs in transient fault recovery schemes for redundant multithreaded processors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4297 LNCS, Issue , 2006, Pages 135-147

  Sharkey, Joseph ^a   Abu Ghazeleh, Nayef ^a   Ponomarev, Dmitry ^a   Ghose, Kanad ^a   Aggarwal, Aneesh ^a  

^a State University of New York   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL APPROACH; DESIGN COMPLEXITY; DOWN-SCALING; FAULT RECOVERY; FEATURE SIZES; MULTITHREADED PROCESSORS; NEW TECHNOLOGIES; RECOVERY SCHEME; SOFT ERROR; SUPPLY VOLTAGES; TRANSIENT ERRORS; TRANSIENT FAULTS;

ERROR CORRECTION; FAULT DETECTION; MACHINE DESIGN; MICROPROCESSOR CHIPS;

ERROR DETECTION;

EID: 77049091362     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11945918_18     Document Type: Conference Paper

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