Trade-offs in transient fault recovery schemes for redundant multithreaded processors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4297 LNCS, Issue , 2006, Pages 135-147

  Sharkey, Joseph ^a   Abu Ghazeleh, Nayef ^a   Ponomarev, Dmitry ^a   Ghose, Kanad ^a   Aggarwal, Aneesh ^a  

^a State University of New York at Binghamton   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL APPROACH; DESIGN COMPLEXITY; DOWN-SCALING; FAULT RECOVERY; FEATURE SIZES; MULTITHREADED PROCESSORS; NEW TECHNOLOGIES; RECOVERY SCHEME; SOFT ERROR; SUPPLY VOLTAGES; TRANSIENT ERRORS; TRANSIENT FAULTS;

ERROR CORRECTION; FAULT DETECTION; MACHINE DESIGN; MICROPROCESSOR CHIPS;

ERROR DETECTION;

EID: 77049091362     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11945918_18     Document Type: Conference Paper

References (24)

1. T. Austin, "DIVA: a reliable substrate for deep submicron microarchitecture design," Proc. Micro-32, 1999.
2. Qureshi, M., et al, "Microarchitecture-Based Introspection: A Technique for Transient Fault Tolerance in Microprocessors", in DSN 2005.
3. J. G. Holm, and P. Banerjee, "Low cost concurrent error detection in a VLIW architecture using replicated instructions" Proc. ICPP-21, 1992.
4. M. Gomaa, et. al., "Transient-Fault Recovery for Chip Multiprocessors," Proc. ISCA-30, 2003.
5. M. Gomaa, T.N.Vijaykumar, "Opportunistic Transient Fault Detection", ISCA 2005
6. J. Ray, J. Hoe, and B. Falsafi, "Dual use of superscalar datapath for transient-fault detection and recovery," Proc. Micro-34, 2001.
7. S. Reinhardt, and S. Mukherjee, "Transient fault detection via simultaneous multithreading," Proc. ISCA-27, June 2000.
8. E. Rotenberg, "AR-SMT: A microarchitectural approach to fault tolerance in microprocessors," Proc. 29th Intl. Symp. On Fault-Tolerant Computing Systems, 1999.
9. J.Smolens, et. al., "Efficient Resource sharing in Concurrent error detecting Superscalar microarchitectures ," Proc. Micro- 37, 2004.
10. K. Sundaramoorthy, Z. Purser, and E. Rotenberg, "Slipstream processors: Improving both performance and fault tolerance," In Proc. Micro-33, December 2000.
11. T. Vijaykumar, I. Pomeranz, and K. Cheng, "Transient-fault recovery using simultaneous multithreading," Proc. ISCA-29, 2002.
12. J. Sharkey. "M-Sim: A Flexible, Multi-threaded Simulation Environment." Tech. Report CS-TR-05-DP1, Department of Computer Science, SUNY Binghamton, 2005.
13. D. Tullsen, et al. "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor." in Proc International Symposium on Computer Architecture, 1996.
14. P. Shivakumar, et al. "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic", in Proc DSN, 2002.
15. S. Mukherjee, et al. "Detailed Design and Evaluation of Redundant Multithreading Alternatives", in Proc ISCA 2002.
16. M. Gomaa, et al. "Transient-fault Recovery for Chip Multiprocessors" in Proc ISCA 2003.
17. Compaq zComputer Corporation, "Data Integrity for Compaq Non-Stop Himalaya Servers", 1999.
18. T. Slegel, et al. "IBM's S/390 G5 Microprocessor Design", IEEE Micro, 1999.
19. D. Ponomarev, et al., "Reducing Datapath Energy through the Isolation of Short-Lived Operands", Proc. PACT 2003.
20. N. Abu-Ghazeleh, et al., "Exploiting Short-Lived Values for Low-Overhead Transient Fault Recovery", Proc. ASGI 2006.
21. J. Martinez, et al., "Cherry: Checkpointed Early Resource Recycling in Out-of-Order Processors", Proc. MICRO 2002.
22. O.Ergin, et al., "Increasing Processor Performance through Early Register Release", Proc. ICCD 2004.
23. M. Kirman, et al., "Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors", Proc. MICRO 2005.
24. J. Smolens, et al, "Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth", Proc. ASPLOS 2004.