A PVT tolerant 10 to 500 MHz all-digital phase-locked loop with coupled TDC and DCO

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 2, 2010, Pages 314-321

  Liu, Wei ^a   Li, Wei ^a,b   Ren, Peng ^b   Lin, Chinglong ^b   Zhang, Shengdong ^a   Wang, Yangyuan ^a  

^a PEKING UNIVERSITY   (China)

^b SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION   (China)

Author keywords

All digital phase locked loop (ADPLL); Digitally controlled oscillator (DCO); Free running ring oscillator (FRO); Time domain; Time to digital converter (TDC)

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; DIGITALLY CONTROLLED OSCILLATORS; RING OSCILLATOR; TIME DOMAIN; TIME TO DIGITAL CONVERTERS;

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; FREQUENCY CONVERTERS; FREQUENCY DIVIDING CIRCUITS; OPTICAL DEVICES; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TIME DOMAIN ANALYSIS;

OSCILLATORS (ELECTRONIC);

EID: 76849110031     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2038127     Document Type: Article

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