Network-on-chip architecture design based on mesh-of-tree deterministic routing topology

International Journal of High Performance Systems Architecture

Volumn 1, Issue 3, 2008, Pages 163-182

  Kundu, Santanu ^a   Chattopadhyay, Santanu ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Deterministic routing; Dual clock FIFO; Globally asynchronous locally synchronous; Interconnection network; Mesh of tree; Network on chip; System on chip

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; FORESTRY; INTEGRATED CIRCUIT INTERCONNECTS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MESH GENERATION; NETWORK ARCHITECTURE; NETWORK ROUTING; NETWORK-ON-CHIP; REUSABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SERVERS; SYSTEM-ON-CHIP;

DETERMINISTIC ROUTING; DUAL CLOCK FIFO; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; MESH OF TREE (MOT); MESH OF TREES; NETWORK-ON-CHIP ARCHITECTURES; NETWORK-ON-CHIP(NOC); NOC ARCHITECTURES;

INTEGRATED CIRCUIT DESIGN;

EID: 73849125198     PISSN: 17516528     EISSN: 17516536     Source Type: Journal    
DOI: 10.1504/IJHPSA.2008.021797     Document Type: Article

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