High-throughput switch-based interconnect for future SoCs

Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Volumn , Issue , 2003, Pages 304-310

  Pande, P P ^a   Grecu, C ^a   Ivanov, A ^a   Saleh, R ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Degradation; Delay; Intellectual property; Multiprocessor interconnection networks; Network on a chip; Signal design; System on a chip; Throughput; Wire; Wiring

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DEGRADATION; DESIGN; ELECTRIC WIRING; INTEGRATED CIRCUIT DESIGN; INTELLECTUAL PROPERTY; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; SWITCHING CIRCUITS; SYSTEM-ON-CHIP; THROUGHPUT; TRANSISTORS; WIRE;

DELAY; NETWORK ON A CHIP; NETWORK-CENTRIC APPROACH; ON-CHIP INTERCONNECTION NETWORK; SEMICONDUCTOR INTELLECTUAL PROPERTY; SIGNAL DESIGN; SYSTEM ON A CHIP; THROUGHPUT DEGRADATION;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 10444263517     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2003.1213053     Document Type: Conference Paper

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