A mesh-of-trees interconnection network for single-chip parallel processing

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2006, Pages 73-80

  Balkan, Aydin O ^a   Qu, Gang ^a   Vishkin, Uzi ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY UNITS; MESH OF TREES; PROCESSING UNITS; SWITCH DELAY; WIRE AREA;

BANDWIDTH; INTERCONNECTION NETWORKS; MESH GENERATION; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; THROUGHPUT;

PARALLEL PROCESSING SYSTEMS;

EID: 34547478190     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2006.6     Document Type: Conference Paper

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