Application of high-k dielectric stacks charge trapping for CMOS technology

Materials Science and Engineering: B

Volumn 166, Issue 2, 2010, Pages 170-173

  Sharma, Satinder K ^a   Prasad, B ^a   Kumar, Dinesh ^a  

^a KURUKSHETRA UNIVERSITY   (India)

Author keywords

Charge trapping detrapping; Dielectric stack

Indexed keywords

CAPACITANCE; CHARGE TRAPPING; HAFNIUM OXIDES; HIGH-K DIELECTRIC; INTERFACE STATES; LEAKAGE CURRENTS; SILICON COMPOUNDS;

% REDUCTIONS; CHARGE TRAPPING-DETRAPPING; CHARGE-TRAPPING; CMOS TECHNOLOGY; DIELECTRIC STACK; HIGH-K DIELECTRIC STACKS; INTERFACES STATE; NEGATIVE-VOLTAGE STRESS; SIO X; TRAPPING STATE;

CMOS INTEGRATED CIRCUITS;

EID: 73249151796     PISSN: 09215107     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mseb.2009.11.002     Document Type: Article

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